Searched refs:DefInst (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp110 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg()); local
111 if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) {
112 if (DefInst->getOperand(1).isImm()) {
115 int64_t Val = DefInst->getOperand(1).getImm();
/external/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp282 Instruction *DefInst; member in struct:__anon14696::EarlyCSE::LoadValue
288 : DefInst(nullptr), Generation(0), MatchingId(-1), IsAtomic(false),
292 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId),
637 if (InVal.DefInst != nullptr &&
644 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType());
647 << " to: " << *InVal.DefInst << '\n');
715 if (InVal.DefInst &&
716 InVal.DefInst == getOrCreateResult(Inst, InVal.DefInst->getType()) &&
/external/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp400 MachineInstr *DefInst = LastDef[Reg]; local
401 if (!DefInst)
403 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
408 MachineBasicBlock::iterator It(DefInst);
419 PotentiallyNewifiableTFR.insert(DefInst);
/external/swiftshader/third_party/subzero/src/
H A DIceRegAlloc.cpp519 const Inst *DefInst = VMetadata->getFirstDefinitionSingleBlock(Iter.Cur); local
520 if (DefInst == nullptr)
523 assert(DefInst->getDest() == Iter.Cur);
525 DefInst->isVarAssign() && !VMetadata->isMultiDef(Iter.Cur);
526 FOREACH_VAR_IN_INST(SrcVar, *DefInst) {

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