Searched refs:FPCR (Results 1 - 12 of 12) sorted by relevance

/external/v8/src/arm64/
H A Ddisasm-arm64.cc1170 case FPCR: form = "'Xt, fpcr"; break;
1179 case FPCR: form = "fpcr, 'Xt"; break;
H A Dsimulator-arm64.cc89 case FPCR:
411 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR);
1114 PrintSystemRegister(FPCR);
1187 case FPCR: {
2898 // Convert double-to-float as the processor would, assuming that FPCR.FZ
3249 case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break;
3260 case FPCR:
3262 LogSystemRegister(FPCR);
H A Dconstants-arm64.h213 /* FPCR */ \
218 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
381 FPCR = ((0x1 << SysO0_offset) | enumerator in enum:v8::internal::SystemRegister
H A Dmacro-assembler-arm64.cc1373 Mrs(fpcr, FPCR);
/external/valgrind/VEX/priv/
H A Dhost_arm64_defs.c1170 i->ARM64in.FPCR.toFPCR = toFPCR;
1171 i->ARM64in.FPCR.iReg = iReg;
1760 if (i->ARM64in.FPCR.toFPCR) {
1762 ppHRegARM64(i->ARM64in.FPCR.iReg);
1765 ppHRegARM64(i->ARM64in.FPCR.iReg);
2173 if (i->ARM64in.FPCR.toFPCR)
2174 addHRegUse(u, HRmRead, i->ARM64in.FPCR.iReg);
2176 addHRegUse(u, HRmWrite, i->ARM64in.FPCR.iReg);
2422 i->ARM64in.FPCR.iReg = lookupHRegRemap(m, i->ARM64in.FPCR
[all...]
H A Dhost_arm64_defs.h812 /* Move a 32-bit value to/from the FPCR */
816 } FPCR; member in union:__anon28205::__anon28206
/external/vixl/src/aarch64/
H A Dsimulator-aarch64.cc56 case FPCR:
107 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR);
595 PrintSystemRegister(FPCR);
856 case FPCR: {
2676 break; // Use FPCR rounding mode.
2893 case FPCR:
2907 case FPCR:
2909 LogSystemRegister(FPCR);
3129 break; // Use FPCR rounding mode.
H A Dconstants-aarch64.h181 /* FPCR */ \
186 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
358 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value enumerator in enum:vixl::aarch64::SystemRegister
/external/llvm/test/MC/AArch64/
H A Dbasic-a64-instructions.s3827 msr FPCR, x12
4081 // CHECK: msr {{fpcr|FPCR}}, x12 // encoding: [0x0c,0x44,0x1b,0xd5]
4375 mrs x9, FPCR
4676 // CHECK: mrs x9, {{fpcr|FPCR}} // encoding: [0x09,0x44,0x3b,0xd5]
/external/vixl/test/aarch64/
H A Dtest-assembler-aarch64.cc11245 // VIXL only supports the round-to-nearest FPCR mode, so this test has the
11599 // VIXL only supports the round-to-nearest FPCR mode, and it doesn't support
13279 // Read the default FPCR.
13280 __ Mrs(x6, FPCR);
13290 // FPCR
13291 // The default FPCR on Linux-based platforms is 0.
13299 // All FPCR fields that must be implemented: AHP, DN, FZ, RMode
13302 // All FPCR fields (including fields which may be read-as-zero):
13333 // All core FPCR fields must be writable.
13335 __ Msr(FPCR, x
[all...]
H A Dtest-disasm-aarch64.cc2791 COMPARE(mrs(x15, FPCR), "mrs x15, fpcr");
2806 COMPARE(msr(FPCR, x15), "msr fpcr, x15");
/external/valgrind/memcheck/
H A Dmc_machine.c1032 if (o == GOF(FPCR) && sz == 4) return -1; // untracked

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