/external/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.h | 26 class MCOperand; 46 MCOperand createRegOperand(unsigned int RegId) const; 47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const; 48 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const; 50 MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const; 57 MCOperand decodeOperand_VGPR_32(unsigned Val) const; 58 MCOperand decodeOperand_VS_32(unsigned Val) const; 59 MCOperand decodeOperand_VS_64(unsigned Val) const; 61 MCOperand decodeOperand_VReg_64(unsigned Val) const; 62 MCOperand decodeOperand_VReg_9 [all...] |
H A D | AMDGPUDisassembler.cpp | 44 addOperand(MCInst &Inst, const MCOperand& Opnd) { 169 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 174 // return MCOperand::createError(V); 175 return MCOperand(); 179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 180 return MCOperand::createReg(RegId); 184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 194 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 233 MCOperand AMDGPUDisassemble [all...] |
/external/capstone/ |
H A D | MCInst.h | 10 // This file contains the declaration of the MCInst and MCOperand classes, which 29 typedef struct MCOperand MCOperand; typedef in typeref:struct:MCOperand 31 /// MCOperand - Instances of this class represent operands of the MCInst class. 33 struct MCOperand { struct 49 bool MCOperand_isValid(const MCOperand *op); 51 bool MCOperand_isReg(const MCOperand *op); 53 bool MCOperand_isImm(const MCOperand *op); 55 bool MCOperand_isFPImm(const MCOperand *op); 57 bool MCOperand_isInst(const MCOperand *o [all...] |
H A D | MCInst.c | 32 void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) 37 //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand)); 64 MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) 75 void MCInst_addOperand2(MCInst *inst, MCOperand *Op) 82 void MCOperand_Init(MCOperand *op) 88 bool MCOperand_isValid(const MCOperand *op) 93 bool MCOperand_isReg(const MCOperand *op) 98 bool MCOperand_isImm(const MCOperand *op) 103 bool MCOperand_isFPImm(const MCOperand *op) 109 unsigned MCOperand_getReg(const MCOperand *o [all...] |
/external/llvm/test/MC/Lanai/ |
H A D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13> 11 ! CHECK-NEXT: <MCOperand Reg:14> 12 ! CHECK-NEXT: <MCOperand Imm:0> 13 ! CHECK-NEXT: <MCOperand Imm:0> 18 ! CHECK-NEXT: <MCOperand Reg:13> 19 ! CHECK-NEXT: <MCOperand Reg:13> 20 ! CHECK-NEXT: <MCOperand Imm:0> 21 ! CHECK-NEXT: <MCOperand Imm:0> 26 ! CHECK-NEXT: <MCOperand Reg:13> 27 ! CHECK-NEXT: <MCOperand Re [all...] |
H A D | conditional_inst.s | 10 ! CHECK-NEXT: <MCOperand Reg:12>> 16 ! CHECK-NEXT: <MCOperand Imm:4660> 22 ! CHECK-NEXT: <MCOperand Imm:2000> 23 ! CHECK-NEXT: <MCOperand Imm:13> 30 ! CHECK-NEXT: <MCOperand Expr:(jump1)> 31 ! CHECK-NEXT: <MCOperand Imm:13> 37 ! CHECK-NEXT: <MCOperand Expr:(jump2)> 38 ! CHECK-NEXT: <MCOperand Imm:10> 46 ! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)> 52 ! CHECK-NEXT: <MCOperand Re [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg)); 39 Inst.addOperand(MCOperand::createImm(Val)); 45 Inst.addOperand(MCOperand::createFPImm(Val)); 51 Inst.addOperand(MCOperand::createExpr(Val)); 57 Inst.addOperand(MCOperand::createInst(Val)); 62 MCInstBuilder &addOperand(const MCOperand &Op) {
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H A D | MCInst.h | 10 // This file contains the declaration of the MCInst and MCOperand classes, which 33 class MCOperand { class in namespace:llvm 53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} function in class:llvm::MCOperand 111 static MCOperand createReg(unsigned Reg) { 112 MCOperand Op; 117 static MCOperand createImm(int64_t Val) { 118 MCOperand Op; 123 static MCOperand createFPImm(double Val) { 124 MCOperand Op; 129 static MCOperand createExp [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64MCInstLower.h | 21 class MCOperand; 38 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const; 41 MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO, 43 MCOperand lowerSymbolOperandELF(const MachineOperand &MO, 45 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
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/external/swiftshader/third_party/LLVM/include/llvm/MC/ |
H A D | MCInst.h | 10 // This file contains the declaration of the MCInst and MCOperand classes, which 29 /// MCOperand - Instances of this class represent operands of the MCInst class. 31 class MCOperand { class in namespace:llvm 49 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} function in class:llvm::MCOperand 97 static MCOperand CreateReg(unsigned Reg) { 98 MCOperand Op; 103 static MCOperand CreateImm(int64_t Val) { 104 MCOperand Op; 109 static MCOperand CreateFPImm(double Val) { 110 MCOperand O [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsMCInstLower.h | 19 class MCOperand; 34 MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const; 37 MCOperand LowerSymbolOperand(const MachineOperand &MO, 39 MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
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/external/llvm/lib/Target/BPF/ |
H A D | BPFMCInstLower.cpp | 32 MCOperand BPFMCInstLower::LowerSymbolOperand(const MachineOperand &MO, 40 return MCOperand::createExpr(Expr); 49 MCOperand MCOp; 58 MCOp = MCOperand::createReg(MO.getReg()); 61 MCOp = MCOperand::createImm(MO.getImm()); 64 MCOp = MCOperand::createExpr(
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H A D | BPFMCInstLower.h | 19 class MCOperand; 37 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcMCInstLower.cpp | 30 static MCOperand LowerSymbolOperand(const MachineInstr *MI, 65 return MCOperand::createExpr(expr); 68 static MCOperand LowerOperand(const MachineInstr *MI, 76 return MCOperand::createReg(MO.getReg()); 79 return MCOperand::createImm(MO.getImm()); 91 return MCOperand(); 103 MCOperand MCOp = LowerOperand(MI, MO, AP);
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/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 577 MI.addOperand(MCOperand::createImm(tmp)); 583 MI.addOperand(MCOperand::createImm(0)); 617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 622 MI.addOperand(MCOperand::createImm(Imm)); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 649 MI.addOperand(MCOperand [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreMCInstLower.h | 18 class MCOperand; 34 MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const; 37 MCOperand LowerSymbolOperand(const MachineOperand &MO,
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H A D | XCoreMCInstLower.cpp | 35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, 71 return MCOperand::createExpr(MCSym); 78 return MCOperand::createExpr(Add); 81 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, 90 return MCOperand::createReg(MO.getReg()); 92 return MCOperand::createImm(MO.getImm() + offset); 104 return MCOperand(); 112 MCOperand MCOp = LowerOperand(MO);
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsMCInstLower.h | 19 class MCOperand; 38 MCOperand LowerSymbolOperand(const MachineOperand &MO, 40 MCOperand LowerOperand(const MachineOperand& MO) const;
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXAsmPrinter.h | 25 class MCOperand; 45 MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol); 46 MCOperand lowerOperand(const MachineOperand &MO);
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H A D | PTXMCInstLower.cpp | 28 MCOperand MCOp;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); 985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 986 BrInst.addOperand(MCOperand::CreateReg(0)); 1031 Inst.addOperand(MCOperand::CreateReg(Dest)); 1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); 1034 Inst.addOperand(MCOperand::CreateImm(pred)); 1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); 1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1248 TmpInst.addOperand(MCOperand [all...] |
H A D | ARMMCInstLower.cpp | 26 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO, 63 return MCOperand::CreateExpr(Expr); 68 MCOperand &MCOp) { 78 MCOp = MCOperand::CreateReg(MO.getReg()); 81 MCOp = MCOperand::CreateImm(MO.getImm()); 84 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( 107 MCOp = MCOperand::CreateFPImm(Val.convertToDouble()); 121 MCOperand MCOp;
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 24 class MCOperand; 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZMCInstLower.h | 19 class MCOperand; 35 // Return an MCOperand for MO. 36 MCOperand lowerOperand(const MachineOperand& MO) const;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 256 mcInst.addOperand(MCOperand::CreateImm(immediate)); 287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 316 MCOperand baseReg; 317 MCOperand scaleAmount; 318 MCOperand indexReg; 319 MCOperand displacement; 320 MCOperand segmentRe [all...] |