Searched refs:MCOperand_CreateReg0 (Results 1 - 11 of 11) sorted by relevance

/external/capstone/arch/Mips/
H A DMipsDisassembler.c551 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
587 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
589 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
626 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
628 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
667 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
669 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
711 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
714 MCOperand_CreateReg0(M
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/external/capstone/arch/X86/
H A DX86Disassembler.c75 MCOperand_CreateReg0(mcInst, llvmRegnum);
105 MCOperand_CreateReg0(mcInst, baseRegNo);
107 MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]);
129 MCOperand_CreateReg0(mcInst, baseRegNo);
279 MCOperand_CreateReg0(mcInst, X86_XMM0 + ((uint32_t)immediate >> 4));
282 MCOperand_CreateReg0(mcInst, X86_YMM0 + ((uint32_t)immediate >> 4));
285 MCOperand_CreateReg0(mcInst, X86_ZMM0 + ((uint32_t)immediate >> 4));
305 MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]);
334 MCOperand_CreateReg0(mcInst, X86_##x); break;
378 MCOperand_CreateReg0(mcIns
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/external/capstone/arch/SystemZ/
H A DSystemZDisassembler.c44 MCOperand_CreateReg0(Inst, (unsigned)RegNo);
192 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
205 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
218 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
220 MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
233 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
235 MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
248 MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
/external/capstone/arch/PowerPC/
H A DPPCDisassembler.c157 MCOperand_CreateReg0(Inst, Regs[RegNo]);
276 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
288 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
305 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
310 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
324 MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]);
/external/capstone/arch/Sparc/
H A DSparcDisassembler.c96 MCOperand_CreateReg0(Inst, Reg);
110 MCOperand_CreateReg0(Inst, Reg);
124 MCOperand_CreateReg0(Inst, Reg);
138 MCOperand_CreateReg0(Inst, Reg);
155 MCOperand_CreateReg0(Inst, Reg);
166 MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);
/external/capstone/
H A DMCInst.h78 void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
H A DMCInst.c150 void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) function
/external/capstone/arch/AArch64/
H A DAArch64Disassembler.c290 MCOperand_CreateReg0(Inst, Register);
324 MCOperand_CreateReg0(Inst, Register);
348 MCOperand_CreateReg0(Inst, Register);
372 MCOperand_CreateReg0(Inst, Register);
396 MCOperand_CreateReg0(Inst, Register);
420 MCOperand_CreateReg0(Inst, Register);
437 MCOperand_CreateReg0(Inst, Register);
462 MCOperand_CreateReg0(Inst, Register);
479 MCOperand_CreateReg0(Inst, Register);
503 MCOperand_CreateReg0(Ins
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/external/capstone/arch/ARM/
H A DARMDisassembler.c419 MCOperand_CreateReg0(Inst, 0);
421 MCOperand_CreateReg0(Inst, ARM_CPSR);
570 //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR));
910 MCOperand_CreateReg0(Inst, Register);
933 MCOperand_CreateReg0(Inst, ARM_APSR_NZCV);
967 MCOperand_CreateReg0(Inst, RegisterPair);
998 MCOperand_CreateReg0(Inst, Register);
1031 MCOperand_CreateReg0(Inst, Register);
1054 MCOperand_CreateReg0(Inst, Register);
1091 MCOperand_CreateReg0(Ins
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H A DARMInstPrinter.c683 MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
/external/capstone/arch/XCore/
H A DXCoreDisassembler.c153 MCOperand_CreateReg0(Inst, Reg);
166 MCOperand_CreateReg0(Inst, Reg);

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