Searched refs:MEM_MASK (Results 1 - 4 of 4) sorted by relevance
/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeTILEGX_64.c | 87 #define MEM_MASK 0x1f macro 1301 FAIL_IF(PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, ADDR_TMP_mapped)); 1303 FAIL_IF(PB2(data_transfer_insts[flags & MEM_MASK], ADDR_TMP_mapped, reg_ar)); 1350 if ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) 1371 return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped); 1373 return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar); 1382 return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, TMP_REG3_mapped); 1384 return PB2(data_transfer_insts[flags & MEM_MASK], TMP_REG3_mapped, reg_ar); 1389 return PB2(data_transfer_insts[flags & MEM_MASK], reg_ar, tmp_ar); 1391 return PB2(data_transfer_insts[flags & MEM_MASK], tmp_a [all...] |
H A D | sljitNativeSPARC_common.c | 402 #define MEM_MASK 0x1f macro 523 FAIL_IF(push_inst(compiler, data_transfer_insts[flags & MEM_MASK] 524 | ((flags & MEM_MASK) <= GPR_REG ? D(reg) : DA(reg)) 526 ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? DR(reg) : MOVABLE_INS)); 581 else if ((flags & LOAD_DATA) && ((flags & MEM_MASK) <= GPR_REG) && reg != base && reg != OFFS_REG(arg)) 602 else if ((flags & LOAD_DATA) && ((flags & MEM_MASK) <= GPR_REG) && reg != base) 610 dest = ((flags & MEM_MASK) <= GPR_REG ? D(reg) : DA(reg)); 611 delay_slot = ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? DR(reg) : MOVABLE_INS; 613 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | dest | S1(arg2) | IMM(0), delay_slot); 615 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | des [all...] |
H A D | sljitNativeMIPS_common.c | 505 #define MEM_MASK 0x1f macro 709 FAIL_IF(push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(arg & REG_MASK) 710 | TA(reg_ar) | IMM(argw), ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? reg_ar : MOVABLE_INS)); 752 if ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) { 773 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 779 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(TMP_REG3) | TA(reg_ar), delay_slot); 782 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot); 788 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(base) | TA(reg_ar), delay_slot); 808 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | SA(tmp_ar) | TA(reg_ar), delay_slot); 811 return push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | [all...] |
H A D | sljitNativePPC_common.c | 532 #define MEM_MASK 0x7f macro 722 ((inst) | (((flags) & MEM_MASK) <= GPR_REG ? D(reg) : FD(reg))) 726 (((inst) & ~(INT_ALIGNED | UPDATE_REQ)) | (((flags) & MEM_MASK) <= GPR_REG ? D(reg) : FD(reg))) 862 inst = data_transfer_insts[(inp_flags | INDEXED) & MEM_MASK]; 872 inst = data_transfer_insts[inp_flags & MEM_MASK]; 887 inst = data_transfer_insts[inp_flags & MEM_MASK]; 958 tmp_r = ((inp_flags & LOAD_DATA) && ((inp_flags) & MEM_MASK) <= GPR_REG) ? reg : TMP_REG1; 982 inst = data_transfer_insts[(inp_flags | INDEXED) & MEM_MASK]; 990 inst = data_transfer_insts[inp_flags & MEM_MASK]; 1063 inst = data_transfer_insts[(inp_flags | INDEXED) & MEM_MASK]; [all...] |
Completed in 130 milliseconds