Searched refs:PrevReg (Results 1 - 6 of 6) sorted by relevance
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.cpp | 226 if (unsigned PrevReg = Result.getRegisterForVar(Var)) 227 dropRegDescribedVar(RegVars, PrevReg, Var);
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/external/llvm/lib/CodeGen/ |
H A D | MachinePipeliner.cpp | 412 unsigned PrevReg = 0); 2670 unsigned PrevReg = 0; local 2672 PrevReg = VRMap[PrevStage - np][LoopVal]; 2674 Def, NewReg, PrevReg); 3249 unsigned NewReg, unsigned PrevReg) { 3277 if (PrevReg && InProlog) 3278 ReplaceReg = PrevReg; 3279 else if (PrevReg && !Schedule.isLoopCarried(this, *Phi) && 3281 ReplaceReg = PrevReg; 3327 unsigned PrevReg local 3246 rewriteScheduledInstr( MachineBasicBlock *BB, SMSchedule &Schedule, InstrMapTy &InstrMap, unsigned CurStageNum, unsigned PhiNum, MachineInstr *Phi, unsigned OldReg, unsigned NewReg, unsigned PrevReg) argument [all...] |
H A D | RegAllocGreedy.cpp | 662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { argument 666 if (PhysReg == PrevReg) 682 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
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/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 500 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); local 513 PrevReg = MCRegOp; 536 TmpInst.addOperand(PrevReg);
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1119 int PrevReg = *RegList.List->begin(); local 1122 if ( Reg != PrevReg + 1) 1124 PrevReg = Reg; 4647 unsigned PrevReg = Mips::NoRegister; local 4666 unsigned TmpReg = PrevReg + 1; 4675 PrevReg = TmpReg; 4682 if ((PrevReg == Mips::NoRegister) && 4695 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && 4719 PrevReg [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 2982 int64_t PrevReg = FirstReg; 2997 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg); 3020 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) 3023 PrevReg = Reg;
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