Searched refs:RegClassID (Results 1 - 6 of 6) sorted by relevance
/external/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.h | 44 const char* getRegClassName(unsigned RegClassID) const; 47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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H A D | AMDGPUDisassembler.cpp | 163 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 165 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, argument 186 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 188 return errOperand(Val, Twine(getRegClassName(RegClassID)) +
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64A57FPLoadBalancing.cpp | 506 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass; local 507 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); 510 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); 534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 289 unsigned RegClassID; local 296 RegClassID = selectSGPRVectorRegClassID(NumVectorElts); 303 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break; 306 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID; 308 RegClassID = AMDGPU::R600_Reg128RegClassID; 315 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); 330 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 686 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg); 1026 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, argument 1028 switch (RegClassID) { 1062 int RegClassID = -1; local 1083 if (RegClassID != -1 && 1084 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { 1090 RegClassID = X86::GR64RegClassID; 1092 RegClassID = X86::GR32RegClassID; 1094 RegClassID = X86::GR16RegClassID; 1101 FinalReg = GetSIDIForRegClass(RegClassID, FinalRe [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1559 unsigned RegClassID, 1567 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1558 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
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