Searched refs:RegClasses (Results 1 - 6 of 6) sorted by relevance

/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenRegisters.cpp464 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses(); local
467 for (unsigned rci = RegClasses.size(); rci; --rci) {
468 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
469 RC.SubClasses.resize(RegClasses.size());
473 for (unsigned s = rci; s != RegClasses.size(); ++s) {
476 CodeGenRegisterClass *SubRC = RegClasses[s];
485 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
490 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
491 const BitVector &SC = RegClasses[rci]->getSubClasses();
495 RegClasses[
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H A DCodeGenRegisters.h232 std::vector<CodeGenRegisterClass*> RegClasses; member in class:llvm::CodeGenRegBank
274 return RegClasses;
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp851 auto &RegClasses = RegBank.getRegClasses(); local
854 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
856 RC.SubClasses.resize(RegClasses.size());
860 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
877 for (auto &RC : RegClasses) {
879 auto I = RegClasses.begin();
893 for (auto &RC : RegClasses)
996 RegClasses.emplace_back(*this, RC);
997 addToMaps(&RegClasses
1614 auto &RegClasses = getRegClasses(); local
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H A DCodeGenRegisters.h502 std::list<CodeGenRegisterClass> RegClasses; member in class:llvm::CodeGenRegBank
536 inferMatchingSuperRegClass(RC, RegClasses.begin());
649 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
652 return RegClasses;
/external/swiftshader/third_party/subzero/pydir/
H A Dgen_arm32_reg_tables.py199 RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32), variable
203 for _, RegClass in RegClasses:
208 for _, RegClass in RegClasses:
223 for Name, RegClass in RegClasses:
/external/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringARM32.cpp1550 // RegClasses is a tuple of
1557 const RegClassType RegClasses[] = { local
1562 for (const auto &RegClass : RegClasses) {

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