Searched refs:SchedModel (Results 1 - 25 of 30) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h35 MCSchedModel SchedModel; member in class:llvm::TargetSchedModel
47 TargetSchedModel(): SchedModel(MCSchedModel::GetDefaultSchedModel()), STI(nullptr), TII(nullptr) {}
70 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
91 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
94 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
102 return SchedModel.getNumProcResourceKinds();
107 return SchedModel.getProcResource(PIdx);
114 return SchedModel.getProcResource(PIdx)->Name;
149 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
154 return SchedModel
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H A DScheduleDAGInstrs.h106 TargetSchedModel SchedModel; member in class:llvm::ScheduleDAGInstrs
243 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
247 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
248 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
H A DMachineScheduler.h565 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
581 const TargetSchedModel *SchedModel; member in class:llvm::SchedBoundary
651 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
700 return RetiredMOps * SchedModel->getMicroOpFactor();
708 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
855 const TargetSchedModel *SchedModel);
860 const TargetSchedModel *SchedModel; member in class:llvm::GenericSchedulerBase
866 Context(C), SchedModel(nullptr), TRI(nullptr) {}
H A DMachineTraceMetrics.h74 TargetSchedModel SchedModel; member in class:llvm::MachineTraceMetrics
112 /// This is an array with SchedModel.getNumProcResourceKinds() entries.
115 /// These numbers have already been scaled by SchedModel.getResourceFactor().
372 // where Kinds = SchedModel.getNumProcResourceKinds().
381 unsigned Factor = SchedModel.getLatencyFactor();
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp31 return EnableSchedModel && SchedModel.hasInstrSchedModel();
56 SchedModel = sm;
61 unsigned NumRes = SchedModel.getNumProcResourceKinds();
63 ResourceLCM = SchedModel.IssueWidth;
65 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
69 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
71 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
106 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
117 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
159 return TII->defaultDefLatency(SchedModel, *DefM
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H A DMachineTraceMetrics.cpp60 SchedModel.init(ST.getSchedModel(), &ST, TII);
63 SchedModel.getNumProcResourceKinds());
96 unsigned PRKinds = SchedModel.getNumProcResourceKinds();
107 if (!SchedModel.hasInstrSchedModel())
109 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
114 PI = SchedModel.getWriteProcResBegin(SC),
115 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
126 PRCycles[K] * SchedModel.getResourceFactor(K);
135 unsigned PRKinds = SchedModel.getNumProcResourceKinds();
148 unsigned PRKinds = MTM.SchedModel
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H A DMachineScheduler.cpp1786 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { argument
1788 if (!SchedModel->hasInstrSchedModel())
1790 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1794 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1795 * SchedModel->getMicroOpFactor();
1797 PI = SchedModel->getWriteProcResBegin(SC),
1798 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1800 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1810 SchedModel = smodel;
1812 if (SchedModel
2301 initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) argument
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H A DMachineCombiner.cpp41 MCSchedModel SchedModel; member in class:__anon13926::MachineCombiner
297 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx);
456 SchedModel = STI.getSchedModel();
457 TSchedModel.init(SchedModel, &STI, TII);
H A DScoreboardHazardRecognizer.cpp71 // A nonempty itinerary must have a SchedModel.
72 IssueWidth = ItinData->SchedModel.IssueWidth;
H A DScheduleDAGInstrs.cpp101 SchedModel.init(ST.getSchedModel(), &ST, TII);
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
353 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
462 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
506 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
659 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
669 if (SchedModel.hasInstrSchedModel()) {
672 PI = SchedModel.getWriteProcResBegin(SC),
673 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
674 switch (SchedModel
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H A DTargetInstrInfo.cpp1028 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel, argument
1033 return SchedModel.LoadLatency;
1035 return SchedModel.HighLatency;
1054 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, argument
1057 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1088 return defaultDefLatency(ItinData->SchedModel, DefMI);
1119 defaultDefLatency(ItinData->SchedModel, DefMI));
H A DEarlyIfConversion.cpp592 MCSchedModel SchedModel; member in class:__anon13894::EarlyIfConverter
700 unsigned CritLimit = SchedModel.MispredictPenalty/2;
798 SchedModel = STI.getSchedModel();
H A DMachineLICM.cpp77 TargetSchedModel SchedModel; member in class:__anon13931::MachineLICM
273 SchedModel.init(ST.getSchedModel(), &ST, TII);
985 if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
1013 if (!TII->hasLowDefLatency(SchedModel, MI, i))
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h46 const TargetSchedModel *SchedModel; member in class:llvm::VLIWResourceModel
57 : SchedModel(SM), TotalPackets(0) {
64 Packet.resize(SchedModel->getIssueWidth());
134 const TargetSchedModel *SchedModel; member in struct:llvm::ConvergingVLIWScheduler::VLIWSchedBoundary
155 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
168 SchedModel = smodel;
191 const TargetSchedModel *SchedModel; member in class:llvm::ConvergingVLIWScheduler
206 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
H A DHexagonMachineScheduler.cpp130 if (Packet.size() >= SchedModel->getIssueWidth()) {
204 SchedModel = DAG->getSchedModel();
206 Top.init(DAG, SchedModel);
207 Bot.init(DAG, SchedModel);
281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
282 if (IssueCount + uops > SchedModel->getIssueWidth())
304 unsigned Width = SchedModel->getIssueWidth();
347 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h111 MCSchedModel SchedModel; ///< Basic machine properties. member in class:llvm::InstrItineraryData
118 InstrItineraryData() : SchedModel(MCSchedModel::GetDefaultSchedModel()),
124 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
125 Itineraries(SchedModel.InstrItineraries) {}
/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp33 TargetSchedModel SchedModel; member in class:__anon14177::AArch64StorePairSuppress
83 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
125 SchedModel.init(ST.getSchedModel(), &ST, TII);
131 if (!SchedModel.hasInstrSchedModel()) {
H A DAArch64ConditionalCompares.cpp723 MCSchedModel SchedModel; member in class:__anon14162::AArch64ConditionalCompares
843 unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4;
894 SchedModel = MF.getSubtarget().getSchedModel();
/external/llvm/lib/MC/
H A DMCSubtargetInfo.cpp96 assert(Found->Value && "Missing processor SchedModel value");
102 const MCSchedModel SchedModel = getSchedModelForCPU(CPU); local
103 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
/external/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h119 const TargetSchedModel *SchedModel) const {
H A DTargetInstrInfo.h1266 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1280 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, argument
1290 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
/external/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp147 SchedModel = getSchedModelForCPU(CPUString);
279 return SchedModel.MispredictPenalty;
294 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
H A DARMBaseInstrInfo.h344 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
349 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
H A DARMSubtarget.h331 /// SchedModel - Processor specific instruction costs.
332 MCSchedModel SchedModel; member in class:llvm::ARMSubtarget
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h129 bool hasLowDefLatency(const TargetSchedModel &SchedModel,

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