Searched refs:array_mode (Results 1 - 9 of 9) sorted by relevance
/external/mesa3d/src/amd/addrlib/inc/chip/r800/ |
H A D | si_gb_reg.h | 98 unsigned int array_mode : 4; member in struct:_GB_TILE_MODE_T 130 unsigned int array_mode : 4; member in struct:_GB_TILE_MODE_T
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_dma.c | 147 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; local 169 array_mode = G_009910_ARRAY_MODE(tile_mode); 205 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
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/external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
H A D | nv50_state_validate.c | 26 uint32_t array_size = 0xffff, array_mode = 0; local 52 array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */ 55 assert(mt->layout_3d || !array_mode || array_size == 1); 70 PUSH_DATA (push, array_mode | array_size); 71 nv50->rt_array_mode = array_mode | array_size;
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | evergreen_state.c | 668 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0; local 760 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; 763 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; 766 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; 817 S_030004_ARRAY_MODE(array_mode)); 1172 unsigned format, array_mode; local 1184 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; 1189 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; 1203 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | 3355 unsigned array_mode, lbp local [all...] |
H A D | r600_state.c | 670 unsigned char swizzle[4], array_mode = 0; local 739 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 742 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 745 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 751 S_038000_TILE_MODE(array_mode) | 1022 unsigned level, pitch, slice, format, offset, array_mode; local 1033 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1038 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1045 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); 2823 unsigned array_mode, lbp local [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | r600_texture.c | 193 enum radeon_surf_mode array_mode, 225 array_mode == RADEON_SURF_MODE_2D) { 260 array_mode, surface); 1241 unsigned array_mode; local 1266 array_mode = RADEON_SURF_MODE_2D; 1268 array_mode = RADEON_SURF_MODE_1D; 1270 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; 1272 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride, 190 r600_init_surface(struct r600_common_screen *rscreen, struct radeon_surf *surface, const struct pipe_resource *ptex, enum radeon_surf_mode array_mode, unsigned pitch_in_bytes_override, unsigned offset, bool is_imported, bool is_scanout, bool is_flushed_depth, bool tc_compatible_htile) argument
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/external/mesa3d/src/amd/vulkan/ |
H A D | radv_image.c | 56 unsigned array_mode = radv_choose_tiling(device, create_info); local 79 surface->flags = RADEON_SURF_SET(array_mode, MODE);
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/external/mesa3d/src/amd/addrlib/r800/ |
H A D | ciaddrlib.cpp | 824 // tile_thickness = (array_mode == XTHICK) ? 8 : ((array_mode == THICK) ? 4 : 1) 1250 UINT_32 regArrayMode = gbTileMode.f.array_mode;
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H A D | siaddrlib.cpp | 2540 UINT_32 regArrayMode = gbTileMode.f.array_mode;
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