Searched refs:bgezall (Results 1 - 23 of 23) sorted by relevance

/external/valgrind/none/tests/mips32/
H A Dbranches.stdout.exp264 bgezall :: 4, RSval: 0
265 bgezall :: 5, RSval: 1
266 bgezall :: 8, RSval: -1
267 bgezall :: 9, RSval: -1
268 bgezall :: 10, RSval: -2
269 bgezall :: 11, RSval: -1
270 bgezall :: 10, RSval: 5
271 bgezall :: 13, RSval: -3
272 bgezall :: 12, RSval: 125
273 bgezall
[all...]
/external/valgrind/none/tests/mips64/
H A Dbranches.stdout.exp264 bgezall :: out: 4, RDval: 0, RSval: 0
265 bgezall :: out: 5, RDval: 1, RSval: 1
266 bgezall :: out: 8, RDval: 2, RSval: -1
267 bgezall :: out: 9, RDval: 3, RSval: -1
268 bgezall :: out: 10, RDval: 4, RSval: -2
269 bgezall :: out: 11, RDval: 5, RSval: -1
270 bgezall :: out: 10, RDval: 6, RSval: 5
271 bgezall :: out: 13, RDval: 7, RSval: -3
272 bgezall :: out: 12, RDval: 8, RSval: 125
273 bgezall
[all...]
/external/llvm/test/MC/Mips/
H A Dmips-jump-delay-slots.s92 # CHECK: bgezall $6, 1332
94 bgezall $6,1332
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips2.s19 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips2.s16 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips2.s13 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s32 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s32 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/v8/src/mips/
H A Dassembler-mips.h633 void bgezall(Register rs, int16_t offset);
634 inline void bgezall(Register rs, Label* L) {
635 bgezall(rs, branch_offset(L) >> 2);
H A Ddisasm-mips.cc1452 Format(instr, "bgezall 'rs, 'imm16u -> 'imm16p4s2");
H A Dassembler-mips.cc1447 void Assembler::bgezall(Register rs, int16_t offset) { function in class:v8::Assembler
/external/v8/src/mips64/
H A Dassembler-mips64.h637 void bgezall(Register rs, int16_t offset);
638 inline void bgezall(Register rs, Label* L) {
639 bgezall(rs, branch_offset(L) >> 2);
H A Dassembler-mips64.cc1434 void Assembler::bgezall(Register rs, int16_t offset) { function in class:v8::internal::Assembler
/external/llvm/test/MC/Mips/mips64/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]

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