/external/valgrind/none/tests/mips32/ |
H A D | branches.stdout.exp | 264 bgezall :: 4, RSval: 0 265 bgezall :: 5, RSval: 1 266 bgezall :: 8, RSval: -1 267 bgezall :: 9, RSval: -1 268 bgezall :: 10, RSval: -2 269 bgezall :: 11, RSval: -1 270 bgezall :: 10, RSval: 5 271 bgezall :: 13, RSval: -3 272 bgezall :: 12, RSval: 125 273 bgezall [all...] |
/external/valgrind/none/tests/mips64/ |
H A D | branches.stdout.exp | 264 bgezall :: out: 4, RDval: 0, RSval: 0 265 bgezall :: out: 5, RDval: 1, RSval: 1 266 bgezall :: out: 8, RDval: 2, RSval: -1 267 bgezall :: out: 9, RDval: 3, RSval: -1 268 bgezall :: out: 10, RDval: 4, RSval: -2 269 bgezall :: out: 11, RDval: 5, RSval: -1 270 bgezall :: out: 10, RDval: 6, RSval: 5 271 bgezall :: out: 13, RDval: 7, RSval: -3 272 bgezall :: out: 12, RDval: 8, RSval: 125 273 bgezall [all...] |
/external/llvm/test/MC/Mips/ |
H A D | mips-jump-delay-slots.s | 92 # CHECK: bgezall $6, 1332 94 bgezall $6,1332
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/external/llvm/test/MC/Mips/mips32r6/ |
H A D | invalid-mips2.s | 19 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips64r6/ |
H A D | invalid-mips2.s | 16 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips1/ |
H A D | invalid-mips2.s | 13 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips2/ |
H A D | valid.s | 32 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips3/ |
H A D | valid.s | 32 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips32/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips32r2/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips32r3/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips32r5/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips4/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips5/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/v8/src/mips/ |
H A D | assembler-mips.h | 633 void bgezall(Register rs, int16_t offset); 634 inline void bgezall(Register rs, Label* L) { 635 bgezall(rs, branch_offset(L) >> 2);
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H A D | disasm-mips.cc | 1452 Format(instr, "bgezall 'rs, 'imm16u -> 'imm16p4s2");
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H A D | assembler-mips.cc | 1447 void Assembler::bgezall(Register rs, int16_t offset) { function in class:v8::Assembler
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/external/v8/src/mips64/ |
H A D | assembler-mips64.h | 637 void bgezall(Register rs, int16_t offset); 638 inline void bgezall(Register rs, Label* L) { 639 bgezall(rs, branch_offset(L) >> 2);
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H A D | assembler-mips64.cc | 1434 void Assembler::bgezall(Register rs, int16_t offset) { function in class:v8::internal::Assembler
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/external/llvm/test/MC/Mips/mips64/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips64r2/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips64r3/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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/external/llvm/test/MC/Mips/mips64r5/ |
H A D | valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
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