| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 32 ctc1 $a2,$26
136 # CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
139 # CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
148 # CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
151 # CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
|
| /external/llvm/test/MC/Mips/ |
| H A D | micromips-fpu-instructions.s | 53 # CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
118 # CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
179 ctc1 $6, $0
|
| H A D | mips-fpu-instructions.s | 145 # CHECK: ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44]
180 ctc1 $10,$31
|
| /external/capstone/suite/MC/Mips/ |
| H A D | mips-fpu-instructions.s.cs | 61 0x00,0xf8,0xca,0x44 = ctc1 $10, $31
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 497 __ ctc1(at, FCSR); \
499 __ ctc1(kScratchReg, FCSR); \
521 __ ctc1(at, FCSR); \
523 __ ctc1(kScratchReg, FCSR); \
1610 __ ctc1(zero_reg, FCSR);
1624 __ ctc1(tmp_fcsr, FCSR);
1638 __ ctc1(zero_reg, FCSR);
1652 __ ctc1(tmp_fcsr, FCSR);
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 46 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 49 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 53 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 53 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | valid.s | 53 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | valid.s | 53 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 53 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 53 ctc1 $a2,$26
|
| /external/v8/src/compiler/mips/ |
| H A D | code-generator-mips.cc | 458 __ ctc1(at, FCSR); \
460 __ ctc1(kScratchReg, FCSR); \
484 __ ctc1(at, FCSR); \
486 __ ctc1(kScratchReg, FCSR); \
|
| /external/v8/src/mips/ |
| H A D | disasm-mips.cc | 1350 Format(instr, "ctc1 'rt, 'fs");
|
| H A D | assembler-mips.h | 875 void ctc1(Register rt, FPUControlRegister fs);
|
| H A D | macro-assembler-mips.cc | 2425 ctc1(zero_reg, FCSR);
2446 ctc1(scratch, FCSR);
2466 ctc1(zero_reg, FCSR);
2472 ctc1(scratch2, FCSR);
|
| H A D | code-stubs-mips.cc | 100 __ ctc1(zero_reg, FCSR);
109 __ ctc1(scratch2, FCSR);
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 55 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 55 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 55 ctc1 $a2,$26
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 55 ctc1 $a2,$26
|
| /external/v8/src/mips64/ |
| H A D | assembler-mips64.h | 933 void ctc1(Register rt, FPUControlRegister fs);
|
| H A D | code-stubs-mips64.cc | 98 __ ctc1(zero_reg, FCSR);
107 __ ctc1(scratch2, FCSR);
|
| H A D | macro-assembler-mips64.cc | 2595 ctc1(zero_reg, FCSR);
2616 ctc1(scratch, FCSR);
2636 ctc1(zero_reg, FCSR);
2642 ctc1(scratch2, FCSR);
|