Searched refs:dclz (Results 1 - 14 of 14) sorted by relevance
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips64.s | 9 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips64r2.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64.s | 12 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips64r2.s | 11 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 299 dclz $1, $2 # CHECK: dclz $1, $2 # encoding: [0x58,0x22,0x5b,0x3c]
|
| /external/v8/src/mips64/ |
| H A D | disasm-mips64.cc | 1262 Format(instr, "dclz 'rd, 'rs");
1453 Format(instr, "dclz 'rd, 'rs");
|
| H A D | assembler-mips64.h | 898 void dclz(Register rd, Register rs);
|
| H A D | assembler-mips64.cc | 2479 void Assembler::dclz(Register rd, Register rs) { function in class:v8::internal::Assembler
2481 // dclz instr requires same GPR number in 'rd' and 'rt' fields.
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1037 __ dclz(i.OutputRegister(), i.InputRegister(0));
1069 __ dclz(reg2, reg2);
|
Completed in 96 milliseconds