| /external/llvm/test/MC/Mips/ |
| H A D | macro-ddivu.s | 6 ddivu $25,$11
8 # CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
12 ddivu $24,$12
14 # CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
18 ddivu $25,$0
20 # CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
24 ddivu $0,$9
26 # CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
30 ddivu $0,$0
32 # CHECK-NOTRAP: ddivu
[all...] |
| H A D | macro-ddiv-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| H A D | macro-ddivu-bad.s | 11 ddivu $25, $11
14 ddivu $25, $0
17 ddivu $0,$0
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| H A D | invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | invalid.s | 79 ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
80 ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
81 ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| H A D | valid.s | 59 ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 25 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips64/ |
| H A D | disasm-mips64.cc | 1338 Format(instr, "ddivu 'rs, 'rt");
1341 Format(instr, "ddivu 'rd, 'rs, 'rt");
|
| H A D | assembler-mips64.h | 737 void ddivu(Register rs, Register rt);
741 void ddivu(Register rd, Register rs, Register rt);
|
| H A D | macro-assembler-mips64.cc | 930 ddivu(rs, rt.rm());
935 ddivu(rs, at);
943 ddivu(rs, rt.rm());
946 ddivu(res, rs, rt.rm());
953 ddivu(rs, at);
956 ddivu(res, rs, at);
990 ddivu(rs, rt.rm());
996 ddivu(rs, at);
|
| H A D | assembler-mips64.cc | 1739 void Assembler::ddivu(Register rs, Register rt) { function in class:v8::internal::Assembler
1744 void Assembler::ddivu(Register rd, Register rs, Register rt) { function in class:v8::internal::Assembler
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 71 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 75 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 75 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 80 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 82 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 82 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 82 ddivu $zero,$s0,$s1
|