Searched refs:dmfc1 (Results 1 - 21 of 21) sorted by relevance
| /external/valgrind/none/tests/mips64/ |
| H A D | change_fp_mode.stdout.exp | 24 dmfc1 $t0, $f0 :: t0: 1234567890abcdef
25 dmfc1 $t0, $f1 :: t0: 5a5a
73 dmfc1 $t0, $f0 :: t0: 1234567890abcdef
74 dmfc1 $t0, $f1 :: t0: 1234567890abcdef
122 dmfc1 $t0, $f0 :: t0: 1234567890abcdef
123 dmfc1 $t0, $f1 :: t0: 5a5a
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| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 26 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips4.s | 24 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 24 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 22 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips4.s | 22 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 22 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.cc | 1500 dmfc1(scratch, fd);
1863 dmfc1(scratch1, fs);
1894 dmfc1(t8, fs);
1945 dmfc1(t8, fs);
2002 dmfc1(t8, fs);
2145 dmfc1(rs, scratch);
2152 dmfc1(rs, scratch);
2159 dmfc1(result, scratch);
2193 dmfc1(rs, scratch);
2200 dmfc1(r
[all...] |
| H A D | assembler-mips64.h | 931 void dmfc1(Register rt, FPURegister fs);
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| H A D | macro-assembler-mips64.h | 315 inline void Move(Register dst, FPURegister src) { dmfc1(dst, src); }
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| H A D | assembler-mips64.cc | 2666 void Assembler::dmfc1(Register rt, FPURegister fs) { function in class:v8::internal::Assembler
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| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 510 __ dmfc1(at, i.OutputDoubleRegister()); \
1614 __ dmfc1(i.OutputRegister(), scratch);
1642 __ dmfc1(i.OutputRegister(0), scratch);
1689 __ dmfc1(i.OutputRegister(), i.InputDoubleRegister(0));
2295 __ dmfc1(result, kDoubleCompareReg);
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 207 dmfc1 $9, $f4 # CHECK: dmfc1 $9, $f4 # encoding: [0x55,0x24,0x24,0x3b]
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| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 76 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 80 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 80 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 86 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 88 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 88 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 88 dmfc1 $12,$f13
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| /external/llvm/test/MC/Mips/ |
| H A D | target-soft-float.s | 11 dmfc1 $7, $f2
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