Searched refs:dmtc1 (Results 1 - 21 of 21) sorted by relevance
| /external/valgrind/none/tests/mips64/ |
| H A D | change_fp_mode.stdout.exp | 20 dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
21 dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
69 dmtc1 $t0, $f0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
70 dmtc1 $t0, $f1 :: lo32(f1): 12345678, lo32(f0): 90abcdef
118 dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
119 dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
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| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 27 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips4.s | 25 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 25 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips4.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips5.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.cc | 1489 dmtc1(scratch, fd);
1868 dmtc1(scratch2, fd);
1887 dmtc1(t9, fd);
1913 dmtc1(t9, fd);
1920 dmtc1(rs, fd);
1939 dmtc1(t9, fd);
1964 dmtc1(t9, fd);
1971 dmtc1(rs, fd);
2006 dmtc1(t8, fs);
2027 dmtc1(t
[all...] |
| H A D | assembler-mips64.h | 927 void dmtc1(Register rt, FPURegister fs);
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| H A D | macro-assembler-mips64.h | 317 inline void Move(FPURegister dst, Register src) { dmtc1(src, dst); }
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| H A D | assembler-mips64.cc | 2651 void Assembler::dmtc1(Register rt, FPURegister fs) { function in class:v8::internal::Assembler
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 203 dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b]
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| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 77 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 81 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 81 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 88 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 90 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 90 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 90 dmtc1 $s0,$f14
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| /external/llvm/test/MC/Mips/ |
| H A D | target-soft-float.s | 13 dmtc1 $6, $f2
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| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1524 __ dmtc1(i.InputRegister(0), scratch);
1530 __ dmtc1(i.InputRegister(0), scratch);
1692 __ dmtc1(i.InputRegister(0), i.OutputDoubleRegister());
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