Searched refs:drmCommandWriteRead (Results 1 - 25 of 43) sorted by relevance

12

/external/mesa3d/src/loader/
H A Dpci_id_driver_map.c38 ret = drmCommandWriteRead(fd, DRM_NOUVEAU_GETPARAM, &gp, sizeof(gp));
/external/libdrm/freedreno/msm/
H A Dmsm_bo.c48 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_INFO,
104 ret = drmCommandWriteRead(bo->dev->fd, DRM_MSM_GEM_MADVISE, &req, sizeof(req));
136 ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_NEW,
H A Dmsm_pipe.c45 ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_GET_PARAM,
/external/libdrm/libkms/
H A Dintel.c112 ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_CREATE, &arg, sizeof(arg));
130 ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_SET_TILING, &tile, sizeof(tile));
172 ret = drmCommandWriteRead(bo->base.kms->fd, DRM_I915_GEM_MMAP_GTT, &arg, sizeof(arg));
H A Dradeon.c121 ret = drmCommandWriteRead(kms->fd, DRM_RADEON_GEM_CREATE,
170 ret = drmCommandWriteRead(bo->base.kms->fd, DRM_RADEON_GEM_MMAP,
H A Dexynos.c98 ret = drmCommandWriteRead(kms->fd, DRM_EXYNOS_GEM_CREATE, &arg, sizeof(arg));
H A Dnouveau.c118 ret = drmCommandWriteRead(kms->fd, DRM_NOUVEAU_GEM_NEW, &arg, sizeof(arg));
H A Dvmwgfx.c105 ret = drmCommandWriteRead(bo->base.kms->fd,
/external/libdrm/tests/radeon/
H A Drbo.c72 r = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE,
108 r = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_MMAP,
167 ret = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_WAIT_IDLE,
/external/libdrm/radeon/
H A Dradeon_bo_gem.c108 r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
172 r = drmCommandWriteRead(boi->bom->fd,
228 ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY,
245 r = drmCommandWriteRead(boi->bom->fd,
260 r = drmCommandWriteRead(boi->bom->fd,
357 r = drmCommandWriteRead(boi->bom->fd,
/external/libdrm/tegra/
H A Dtegra.c131 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_CREATE, &args,
259 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_MMAP, &args,
308 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_GET_FLAGS, &args,
332 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_SET_FLAGS, &args,
353 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_GET_TILING, &args,
381 err = drmCommandWriteRead(drm->fd, DRM_TEGRA_GEM_SET_TILING, &args,
/external/libdrm/amdgpu/
H A Damdgpu_bo.c109 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
142 return drmCommandWriteRead(bo->dev->fd,
163 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_METADATA,
177 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_OP,
452 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_MMAP, &args,
520 r = drmCommandWriteRead(bo->dev->fd, DRM_AMDGPU_GEM_WAIT_IDLE,
545 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR,
606 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
628 r = drmCommandWriteRead(list->dev->fd, DRM_AMDGPU_BO_LIST,
672 r = drmCommandWriteRead(handl
[all...]
H A Damdgpu_cs.c80 r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
122 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
153 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
311 r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
/external/libdrm/freedreno/kgsl/
H A Dkgsl_bo.c61 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_ALLOC,
148 ret = drmCommandWriteRead(dev->fd, DRM_KGSL_GEM_CREATE,
241 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
305 ret = drmCommandWriteRead(bo->dev->fd, DRM_KGSL_GEM_GET_BUFINFO,
/external/mesa3d/src/gallium/winsys/svga/drm/
H A Dvmw_screen_ioctl.c101 ret = drmCommandWriteRead(vws->ioctl.drm_fd,
177 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SURFACE,
244 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_CREATE,
366 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GB_SURFACE_REF,
509 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_ALLOC_DMABUF, &arg,
700 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_SIGNALED,
729 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_FENCE_WAIT,
765 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_CREATE_SHADER,
877 ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
886 ret = drmCommandWriteRead(vw
[all...]
/external/libdrm/nouveau/
H A Dabi16.c49 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
70 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
96 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
162 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
358 ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_GEM_NEW,
/external/libdrm/omap/
H A Domap_drm.c143 ret = drmCommandWriteRead(dev->fd, DRM_OMAP_GET_PARAM, &req, sizeof(req));
210 if (drmCommandWriteRead(dev->fd, DRM_OMAP_GEM_NEW, &req, sizeof(req))) {
274 int ret = drmCommandWriteRead(bo->dev->fd, DRM_OMAP_GEM_INFO,
/external/libdrm/etnaviv/
H A Detnaviv_bo.c125 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GEM_NEW,
153 ret = drmCommandWriteRead(bo->dev->fd, DRM_ETNAVIV_GEM_INFO,
H A Detnaviv_gpu.c42 ret = drmCommandWriteRead(dev->fd, DRM_ETNAVIV_GET_PARAM, &req, sizeof(req));
H A Detnaviv_cmd_stream.c197 ret = drmCommandWriteRead(gpu->dev->fd, DRM_ETNAVIV_GEM_SUBMIT,
/external/drm_gralloc/
H A Dgralloc_drm_radeon.c340 ret = drmCommandWriteRead(info->fd, DRM_RADEON_INFO,
452 err = drmCommandWriteRead(info->fd, DRM_RADEON_INFO, &kinfo, sizeof(kinfo));
489 err = drmCommandWriteRead(info->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo));
H A Dgralloc_drm_intel.c447 if (drmCommandWriteRead(info->fd, DRM_I915_GETPARAM, &gp, sizeof(gp)))
453 if (drmCommandWriteRead(info->fd, DRM_I915_GETPARAM, &gp, sizeof(gp)))
H A Dgralloc_drm_pipe.c378 err = drmCommandWriteRead(pm->fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
388 err = drmCommandWriteRead(pm->fd, DRM_RADEON_INFO, &info, sizeof(info));
/external/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c104 if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
136 retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
361 drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
366 retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
H A Dradeon_drm_bo.c68 return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
189 if (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_OP,
362 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va,
435 if (drmCommandWriteRead(bo->rws->fd,
628 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
672 r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
870 drmCommandWriteRead(bo->rws->fd,
931 drmCommandWriteRead(bo->rws->fd,
1072 if (drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
1112 r = drmCommandWriteRead(w
[all...]

Completed in 847 milliseconds

12