Searched refs:drotr (Results 1 - 15 of 15) sorted by relevance

/external/llvm/test/MC/Mips/
H A Drotations64.s111 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
131 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
136 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
139 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
159 # CHECK-64R: drotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xfa]
164 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
182 # CHECK-64R: drotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x7a]
185 # CHECK-64R: drotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x3a]
190 # CHECK-64R: drotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x7a]
195 # CHECK-64R: drotr
[all...]
H A Dmips_directives.s76 # CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
78 drotr $9, $6, 30
H A Dmips64-alu-instructions.s76 # CHECK: drotr $9, $6, 20 # encoding: [0x3a,0x4d,0x26,0x00]
101 drotr $9, $6, 20
/external/llvm/test/MC/Mips/mips5/
H A Dinvalid-mips64r2.s14 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64/
H A Dinvalid-mips64r2.s15 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/capstone/suite/MC/Mips/
H A Dmips64-alu-instructions.s.cs38 0x3a,0x4d,0x26,0x00 = drotr $9, $6, 20
/external/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s96 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
97 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
/external/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s96 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
97 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
/external/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s96 drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
97 drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
/external/llvm/test/MC/Mips/micromips64r6/
H A Dinvalid.s290 drotr $5, $10, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
291 drotr $5, $10, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
H A Dvalid.s300 drotr $5, $10, 8 # CHECK: drotr $5, $10, 8 # encoding: [0x58,0xaa,0x40,0xc0]
/external/v8/src/mips64/
H A Ddisasm-mips64.cc1194 Format(instr, "drotr 'rd, 'rt, 'sa");
H A Dassembler-mips64.h796 void drotr(Register rd, Register rt, uint16_t sa);
H A Dassembler-mips64.cc1875 void Assembler::drotr(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler
H A Dmacro-assembler-mips64.cc1138 drotr(rd, rs, dror_value);

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