Searched refs:dsbh (Results 1 - 13 of 13) sorted by relevance
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | invalid-mips64r2.s | 8 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | invalid-mips64r2.s | 8 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | invalid-mips64r2.s | 8 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 14 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 19 dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 20 dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 272 dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c]
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| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 101 dsbh $v1,$14
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| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 101 dsbh $v1,$14
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| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 101 dsbh $v1,$14
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| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.cc | 1211 dsbh(dest, src);
1216 dsbh(dest, src);
1220 dsbh(dest, src);
1223 dsbh(dest, src);
1233 dsbh(dest, src);
1237 dsbh(dest, src);
1242 dsbh(dest, src);
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| H A D | assembler-mips64.h | 911 void dsbh(Register rd, Register rt);
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| H A D | assembler-mips64.cc | 2577 void Assembler::dsbh(Register rd, Register rt) { function in class:v8::internal::Assembler
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