Searched refs:dshd (Results 1 - 13 of 13) sorted by relevance
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | invalid-mips64r2.s | 9 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | invalid-mips64r2.s | 9 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | invalid-mips64r2.s | 9 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 15 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 20 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 21 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 273 dshd $3, $4 # CHECK: dshd $3, $4 # encoding: [0x58,0x64,0xfb,0x3c]
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| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 102 dshd $v0,$sp
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| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 102 dshd $v0,$sp
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| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 102 dshd $v0,$sp
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| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.cc | 1212 dshd(dest, dest);
1217 dshd(dest, dest);
1221 dshd(dest, dest);
1224 dshd(dest, dest);
1234 dshd(dest, dest);
1238 dshd(dest, dest);
1243 dshd(dest, dest);
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| H A D | assembler-mips64.h | 912 void dshd(Register rd, Register rt);
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| H A D | assembler-mips64.cc | 2582 void Assembler::dshd(Register rd, Register rt) { function in class:v8::internal::Assembler
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