| /external/llvm/test/MC/Mips/ |
| H A D | rotations64.s | 92 # CHECK-64: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
99 # CHECK-64: dsllv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x14]
168 # CHECK-64: dsllv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x14]
174 # CHECK-64: dsllv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x14]
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 85 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
88 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 89 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
92 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 89 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
92 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 96 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
99 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 105 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
108 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 105 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
108 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 105 dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
108 dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 37 dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 33 dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 32 dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 33 dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 31 dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 30 dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 276 dsllv $4, $5, $6 # CHECK: dsllv $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x10]
|
| /external/v8/src/mips64/ |
| H A D | code-stubs-mips64.cc | 1506 __ dsllv(t1, t0, a3);
1508 __ dsllv(t1, a1, a3);
1514 __ dsllv(t1, t2, a3);
|
| H A D | assembler-mips64.h | 793 void dsllv(Register rd, Register rt, Register rs);
|
| H A D | assembler-mips64.cc | 1860 void Assembler::dsllv(Register rd, Register rt, Register rs) { function in class:v8::internal::Assembler
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| H A D | macro-assembler-mips64.cc | 6588 dsllv(mask_reg, t8, mask_reg);
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1244 __ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
|
| /external/v8/src/full-codegen/mips64/ |
| H A D | full-codegen-mips64.cc | 1620 __ dsllv(scratch1, scratch1, scratch2);
|