| /external/llvm/test/MC/Mips/ |
| H A D | rotations64.s | 106 # CHECK-64: dsrl32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xfe]
114 # CHECK-64: dsrl32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfe]
119 # CHECK-64: dsrl32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7e]
124 # CHECK-64: dsrl32 $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3e]
142 # CHECK-64: dsrl32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfe]
147 # CHECK-64: dsrl32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7e]
152 # CHECK-64: dsrl32 $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3e]
197 # CHECK-64: dsrl32 $1, $5, 0 # encoding: [0x00,0x05,0x08,0x3e]
202 # CHECK-64: dsrl32 $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7e]
207 # CHECK-64: dsrl32
[all...] |
| H A D | macro-dla.s | 21 # CHECK: dsrl32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3e]
543 # CHECK: dsrl32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3e]
591 # CHECK: dsrl32 $1, $1, 0 # encoding: [0x00,0x01,0x08,0x3e]
|
| H A D | macro-dli.s | 21 # CHECK: dsrl32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3e]
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 47 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 43 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 42 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 43 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 41 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 40 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 98 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
99 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 102 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
103 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 102 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
103 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 109 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
110 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 118 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
119 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 118 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
119 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 118 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
119 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 308 dsrl32 $3, $4, 5 # CHECK: dsrl32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x48]
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1170 __ dsrl32(reg2, reg1, 0);
1265 __ dsrl32(i.OutputRegister(), i.InputRegister(0),
1850 __ dsrl32(i.OutputRegister(0), i.OutputRegister(0), 0);
2171 __ dsrl32(kScratchReg, i.OutputRegister(), 31);
|
| /external/v8/src/mips64/ |
| H A D | assembler-mips64.h | 802 void dsrl32(Register rt, Register rd, uint16_t sa);
|
| H A D | macro-assembler-mips64.cc | 1241 dsrl32(src, src, 0);
1455 dsrl32(scratch, rd, 0);
4025 dsrl32(src, src, 0);
4036 dsrl32(scratch, scratch, 0);
4038 dsrl32(dst, dst, 0);
|
| H A D | assembler-mips64.cc | 1912 void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler
|
| /external/v8/src/crankshaft/mips64/ |
| H A D | lithium-codegen-mips64.cc | 1079 __ dsrl32(result, dividend, 31);
1083 __ dsrl32(result, result, 32 - shift);
3512 __ dsrl32(result, result, 0);
|