| /external/llvm/test/MC/Mips/ |
| H A D | rotations64.s | 91 # CHECK-64: dsrlv $1, $4, $1 # encoding: [0x00,0x24,0x08,0x16]
98 # CHECK-64: dsrlv $1, $5, $1 # encoding: [0x00,0x25,0x08,0x16]
169 # CHECK-64: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
175 # CHECK-64: dsrlv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x16]
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 97 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
100 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 101 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
104 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 101 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
104 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 108 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
111 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 117 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
120 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 117 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
120 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 117 dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
120 dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips3.s | 49 dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 45 dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 44 dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips3.s | 45 dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips4.s | 43 dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| H A D | invalid-mips5.s | 42 dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 309 dsrlv $1, $3, $3 # CHECK: dsrlv $1, $3, $3 # encoding: [0x58,0x63,0x08,0x50]
|
| /external/v8/src/mips64/ |
| H A D | disasm-mips64.cc | 1228 Format(instr, "dsrlv 'rd, 'rt, 'rs");
|
| H A D | assembler-mips64.h | 795 void dsrlv(Register rd, Register rt, Register rs);
|
| H A D | assembler-mips64.cc | 1870 void Assembler::dsrlv(Register rd, Register rt, Register rs) { function in class:v8::internal::Assembler
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1258 __ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
|
| /external/v8/src/full-codegen/mips64/ |
| H A D | full-codegen-mips64.cc | 1627 __ dsrlv(scratch1, scratch1, scratch2);
|