Searched refs:ld1 (Results 1 - 25 of 115) sorted by relevance

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/external/libmpeg2/common/armv8/
H A Dicv_sad_av8.s78 ld1 {v0.8b}, [x0], x2
79 ld1 {v1.8b}, [x0], x2
80 ld1 {v2.8b}, [x0], x2
81 ld1 {v3.8b}, [x0], x2
84 ld1 {v4.8b}, [x1], x3
85 ld1 {v5.8b}, [x1], x3
86 ld1 {v6.8b}, [x1], x3
87 ld1 {v7.8b}, [x1], x3
H A Dimpeg2_inter_pred.s113 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
117 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
119 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
121 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
123 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
125 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
127 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
129 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
131 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
133 ld1 {v
[all...]
H A Dideint_spatial_filter_av8.s77 ld1 {v0.8b}, [x0], x2
80 ld1 {v1.8b}, [x5]
84 ld1 {v2.8b}, [x5]
98 ld1 {v3.8b}, [x0], x2
101 ld1 {v4.8b}, [x5]
105 ld1 {v5.8b}, [x5]
213 ld1 {v0.s}[0], [x4], x2
214 ld1 {v2.s}[0], [x5], x2
216 ld1 {v0.s}[1], [x6], x2
217 ld1 {v
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/external/libavc/common/armv8/
H A Dih264_default_weighted_pred_av8.s126 ld1 {v0.s}[0], [x0], x3 //load row 1 in source 1
127 ld1 {v0.s}[1], [x0], x3 //load row 2 in source 1
128 ld1 {v2.s}[0], [x1], x4 //load row 1 in source 2
129 ld1 {v2.s}[1], [x1], x4 //load row 2 in source 2
130 ld1 {v1.s}[0], [x0], x3 //load row 3 in source 1
131 ld1 {v1.s}[1], [x0], x3 //load row 4 in source 1
133 ld1 {v3.s}[0], [x1], x4 //load row 3 in source 2
134 ld1 {v3.s}[1], [x1], x4 //load row 4 in source 2
146 ld1 {v0.8b}, [x0], x3 //load row 1 in source 1
147 ld1 {v
[all...]
H A Dih264_iquant_itrans_recon_dc_av8.s133 ld1 {v0.h}[0], [x10]
137 ld1 {v0.h}[0], [x5]
138 ld1 {v1.h}[0], [x6]
139 ld1 {v2.h}[0], [x0]
150 ld1 {v1.s}[0], [x1], x3
151 ld1 {v1.s}[1], [x1], x3
152 ld1 {v2.s}[0], [x1], x3
153 ld1 {v2.s}[1], [x1]
232 ld1 {v0.h}[0], [x0]
243 ld1 {v
[all...]
H A Dih264_inter_pred_luma_copy_av8.s105 ld1 {v0.s}[0], [x0] //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
109 ld1 {v0.s}[0], [x5], x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
112 ld1 {v0.s}[0], [x5], x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
115 ld1 {v0.s}[0], [x5], x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
143 ld1 {v0.8b}, [x0], #8 //vld1_u8(pu1_src_tmp)
146 ld1 {v1.8b}, [x5], x2 //vld1_u8(pu1_src_tmp)
149 ld1 {v2.8b}, [x5], x2 //vld1_u8(pu1_src_tmp)
151 ld1 {v3.8b}, [x5], x2 //vld1_u8(pu1_src_tmp)
175 ld1 { v0.16b}, [x0], #16 //vld1_u8(pu1_src_tmp)
178 ld1 { v
[all...]
H A Dih264_inter_pred_luma_vert_qpel_av8.s136 ld1 {v0.2s, v1.2s}, [x0], x2 // Vector load from src[0_0]
137 ld1 {v2.2s, v3.2s}, [x0], x2 // Vector load from src[1_0]
138 ld1 {v4.2s, v5.2s}, [x0], x2 // Vector load from src[2_0]
139 ld1 {v6.2s, v7.2s}, [x0], x2 // Vector load from src[3_0]
141 ld1 {v8.2s, v9.2s}, [x0], x2 // Vector load from src[4_0]
143 ld1 {v10.2s, v11.2s}, [x0], x2 // Vector load from src[5_0]
153 ld1 {v0.2s, v1.2s}, [x0], x2
165 ld1 {v2.2s, v3.2s}, [x0], x2
169 ld1 {v20.2s, v21.2s}, [x7], x2 // Load for interpolation row 0
184 ld1 {v
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/external/libhevc/common/arm64/
H A Dihevc_inter_pred_chroma_horz_w16out.s121 ld1 {v0.8b},[x4] //coeff = vld1_s8(pi1_coeff)
187 ld1 { v0.2s},[x12],x11 //vector load pu1_src
188 ld1 { v1.2s},[x19],x11 //vector load pu1_src
191 ld1 { v2.2s},[x12],x11 //vector load pu1_src
192 ld1 { v3.2s},[x19],x11 //vector load pu1_src
196 ld1 { v4.2s},[x12],x11 //vector load pu1_src
197 ld1 { v5.2s},[x19],x11 //vector load pu1_src
201 ld1 { v6.2s},[x12],x9 //vector load pu1_src
202 ld1 { v7.2s},[x19],x9 //vector load pu1_src
207 ld1 { v2
[all...]
H A Dihevc_inter_pred_chroma_horz.s125 ld1 {v0.8b},[x4] //coeff = vld1_s8(pi1_coeff)
175 ld1 { v0.2s},[x12],x11 //vector load pu1_src
176 ld1 { v1.2s},[x19],x11 //vector load pu1_src
180 ld1 { v2.2s},[x12],x11 //vector load pu1_src
181 ld1 { v3.2s},[x19],x11 //vector load pu1_src
183 ld1 { v4.2s},[x12],x11 //vector load pu1_src
184 ld1 { v5.2s},[x19],x11 //vector load pu1_src
186 ld1 { v6.2s},[x12],x9 //vector load pu1_src
187 ld1 { v7.2s},[x19],x9 //vector load pu1_src
192 ld1 { v2
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H A Dihevc_inter_pred_luma_horz_w16out.s130 ld1 {v0.8b},[x8] //coeff = vld1_s8(pi1_coeff)
211 ld1 {v20.2s},[x16],x15 //vector load pu1_src
212 ld1 {v21.2s},[x16],x15
213 ld1 {v22.2s},[x8],x15 //vector load pu1_src + src_strd
214 ld1 {v23.2s},[x8],x15
221 ld1 {v20.2s},[x16],x15
222 ld1 {v21.2s},[x16],x15
223 ld1 {v22.2s},[x8],x15
224 ld1 {v23.2s},[x8],x15
231 ld1 {v2
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H A Dihevc_intra_pred_luma_mode_18_34.s134 ld1 {v0.8b},[x8],x6
136 ld1 {v1.8b},[x8],x6
138 ld1 {v2.8b},[x8],x6
139 ld1 {v3.8b},[x8],x6
141 ld1 {v4.8b},[x8],x6
142 ld1 {v5.8b},[x8],x6
143 ld1 {v6.8b},[x8],x6
145 ld1 {v7.8b},[x8],x6
167 ld1 {v0.8b},[x8],x6
171 ld1 {v
[all...]
H A Dihevc_inter_pred_filters_luma_horz.s135 ld1 {v0.8b},[x4] //coeff = vld1_s8(pi1_coeff)
204 ld1 {v0.2s},[x12],x11 //vector load pu1_src
205 ld1 {v1.2s},[x12],x11
206 ld1 {v2.2s},[x12],x11
207 ld1 {v3.2s},[x12],x11
228 ld1 {v4.2s},[x12],x11
230 ld1 {v5.2s},[x12],x11
232 ld1 {v6.2s},[x12],x11
234 ld1 {v7.2s},[x12],x11
236 ld1 {v1
[all...]
H A Dihevc_intra_pred_luma_mode2.s123 ld1 {v0.8b},[x0],x8
126 ld1 {v1.8b},[x10],x8
129 ld1 {v2.8b},[x0],x8
130 ld1 {v3.8b},[x10],x8
133 ld1 {v4.8b},[x0],x8
134 ld1 {v5.8b},[x10],x8
135 ld1 {v6.8b},[x0],x8
138 ld1 {v7.8b},[x10],x8
181 ld1 {v0.8b},[x0],x8
184 ld1 {v
[all...]
H A Dihevc_inter_pred_luma_copy.s101 ld1 {v0.s}[0],[x0] //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
105 ld1 {v0.s}[0],[x9],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
108 ld1 {v0.s}[0],[x9],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
111 ld1 {v0.s}[0],[x9],x2 //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
140 ld1 {v0.8b},[x0],#8 //vld1_u8(pu1_src_tmp)
143 ld1 {v1.8b},[x9],x2 //vld1_u8(pu1_src_tmp)
146 ld1 {v2.8b},[x9],x2 //vld1_u8(pu1_src_tmp)
148 ld1 {v3.8b},[x9],x2 //vld1_u8(pu1_src_tmp)
173 ld1 {v0.16b},[x0],#16 //vld1_u8(pu1_src_tmp)
176 ld1 {v
[all...]
H A Dihevc_intra_pred_chroma_mode_18_34.s136 ld1 {v0.8b, v1.8b},[x8],x6
138 ld1 {v2.8b, v3.8b},[x8],x6
140 ld1 {v4.8b, v5.8b},[x8],x6
142 ld1 {v6.8b, v7.8b},[x8],x6
144 ld1 {v16.8b, v17.8b},[x8],x6
146 ld1 {v18.8b, v19.8b},[x8],x6
148 ld1 {v20.8b, v21.8b},[x8],x6
150 ld1 {v22.8b, v23.8b},[x8],x6
176 ld1 {v0.8b},[x0],x8
179 ld1 {v
[all...]
H A Dihevc_inter_pred_filters_luma_vert_w16inp.s119 ld1 {v0.8b},[x12] //coeff = vld1_s8(pi1_coeff)
151 ld1 {v1.4h},[x3],x2 //src_tmp2 = vld1_u8(pu1_src_tmp)//
152 ld1 {v0.4h},[x0],#8 //src_tmp1 = vld1_u8(pu1_src_tmp)//
154 ld1 {v2.4h},[x3],x2 //src_tmp3 = vld1_u8(pu1_src_tmp)//
156 ld1 {v3.4h},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
158 ld1 {v4.4h},[x3],x2 //src_tmp1 = vld1_u8(pu1_src_tmp)//
160 ld1 {v5.4h},[x3],x2 //src_tmp2 = vld1_u8(pu1_src_tmp)//
162 ld1 {v6.4h},[x3],x2 //src_tmp3 = vld1_u8(pu1_src_tmp)//
164 ld1 {v7.4h},[x3],x2 //src_tmp4 = vld1_u8(pu1_src_tmp)//
169 ld1 {v1
[all...]
H A Dihevc_inter_pred_luma_vert_w16inp_w16out.s128 ld1 {v0.8b},[x12] //coeff = ld1_s8(pi1_coeff)
162 ld1 {v1.4h},[x3],x2 //src_tmp2 = ld1_u8(pu1_src_tmp)//
163 ld1 {v0.4h},[x0], #8 //src_tmp1 = ld1_u8(pu1_src_tmp)//
165 ld1 {v2.4h},[x3],x2 //src_tmp3 = ld1_u8(pu1_src_tmp)//
167 ld1 {v3.4h},[x3],x2 //src_tmp4 = ld1_u8(pu1_src_tmp)//
169 ld1 {v4.4h},[x3],x2 //src_tmp1 = ld1_u8(pu1_src_tmp)//
171 ld1 {v5.4h},[x3],x2 //src_tmp2 = ld1_u8(pu1_src_tmp)//
173 ld1 {v6.4h},[x3],x2 //src_tmp3 = ld1_u8(pu1_src_tmp)//
175 ld1 {v7.4h},[x3],x2 //src_tmp4 = ld1_u8(pu1_src_tmp)//
180 ld1 {v1
[all...]
H A Dihevc_intra_pred_filters_luma_mode_19_to_25.s142 ld1 {v0.s}[0],[x1],#4 // pu1_ref[two_nt + k]
156 ld1 {v0.8b},[x1],#8
157 ld1 {v1.8b},[x1],#8
158 ld1 {v2.8b},[x1],#8
159 ld1 {v3.8b},[x1],#8
168 ld1 {v0.8b},[x1],#8
169 ld1 {v1.8b},[x1],#8
176 ld1 {v0.8b},[x1],#8
256 ld1 {v3.8b},[x6] //loads the row value
273 ld1 {v2
[all...]
H A Dihevc_inter_pred_chroma_vert.s119 ld1 {v0.8b},[x12] //loads pi1_coeff
145 ld1 {v17.8b},[x6],x2 //loads pu1_src
147 ld1 {v5.8b},[x0],#8 //loads src
149 ld1 {v4.8b},[x6],x2 //loads incremented src
151 ld1 {v16.8b},[x6],x2 //loads incremented src
156 ld1 {v18.8b},[x6] //loads the incremented src
187 ld1 {v6.s}[0],[x0] //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp1, 0
190 ld1 {v6.s}[1],[x6],x2 //loads pu1_src_tmp
192 ld1 {v7.s}[1],[x6],x2 //loads pu1_src_tmp
195 ld1 {v
[all...]
H A Dihevc_inter_pred_chroma_vert_w16out.s121 ld1 {v0.8b},[x12] //loads pi1_coeff
148 ld1 {v17.8b},[x6],x2 //loads pu1_src
150 ld1 {v5.8b},[x0],#8 //loads src
152 ld1 {v4.8b},[x6],x2 //loads incremented src
154 ld1 {v16.8b},[x6],x2 //loads incremented src
157 ld1 {v18.8b},[x6] //loads the incremented src
188 ld1 {v6.s}[0],[x0] //vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp1, 0
191 ld1 {v6.s}[1],[x6],x2 //loads pu1_src_tmp
193 ld1 {v7.s}[1],[x6],x2 //loads pu1_src_tmp
196 ld1 {v
[all...]
/external/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s238 ld1 { v0.16b }, [x0]
239 ld1 { v15.8h }, [x15]
240 ld1 { v31.4s }, [sp]
241 ld1 { v0.2d }, [x0]
242 ld1 { v0.8b }, [x0]
243 ld1 { v15.4h }, [x15]
244 ld1 { v31.2s }, [sp]
245 ld1 { v0.1d }, [x0]
246 // CHECK: ld1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x40,0x4c]
247 // CHECK: ld1 { v1
[all...]
H A Dneon-simd-post-ldst-multi-elem.s8 ld1 { v0.16b }, [x0], x1
9 ld1 { v15.8h }, [x15], x2
10 ld1 { v31.4s }, [sp], #16
11 ld1 { v0.2d }, [x0], #16
12 ld1 { v0.8b }, [x0], x2
13 ld1 { v15.4h }, [x15], x3
14 ld1 { v31.2s }, [sp], #8
15 ld1 { v0.1d }, [x0], #8
16 // CHECK: ld1 { v0.16b }, [x0], x1
18 // CHECK: ld1 { v1
[all...]
/external/libavc/encoder/armv8/
H A Dime_distortion_metrics_av8.s108 ld1 {v0.16b}, [x0], x2
109 ld1 {v1.16b}, [x1], x3
110 ld1 {v2.16b}, [x0], x2
111 ld1 {v3.16b}, [x1], x3
119 ld1 {v4.16b}, [x0], x2
120 ld1 {v5.16b}, [x1], x3
121 ld1 {v6.16b}, [x0], x2
122 ld1 {v7.16b}, [x1], x3
191 ld1 {v0.16b}, [x0], x2
192 ld1 {v
[all...]
/external/libxaac/decoder/armv8/
H A Dixheaacd_cos_sin_mod_loop1.s52 ld1 {v0.h}[0] , [x2]
54 ld1 {v0.h}[2] , [x2]
57 ld1 {v2.s}[0], [x0]
60 ld1 {v2.s}[1], [x7]
61 ld1 {v3.s}[0], [x4]
63 ld1 {v3.s}[1], [x7]
89 ld1 {v0.h}[0] , [x2]
91 ld1 {v0.h}[2] , [x2]
94 ld1 {v2.s}[0], [x0]
97 ld1 {v
[all...]
/external/capstone/suite/MC/AArch64/
H A Dneon-simd-post-ldst-multi-elem.s.cs2 0x00,0x70,0xc1,0x4c = ld1 {v0.16b}, [x0], x1
3 0xef,0x75,0xc2,0x4c = ld1 {v15.8h}, [x15], x2
4 0xff,0x7b,0xdf,0x4c = ld1 {v31.4s}, [sp], #16
5 0x00,0x7c,0xdf,0x4c = ld1 {v0.2d}, [x0], #16
6 0x00,0x70,0xc2,0x0c = ld1 {v0.8b}, [x0], x2
7 0xef,0x75,0xc3,0x0c = ld1 {v15.4h}, [x15], x3
8 0xff,0x7b,0xdf,0x0c = ld1 {v31.2s}, [sp], #8
9 0x00,0x7c,0xdf,0x0c = ld1 {v0.1d}, [x0], #8
10 0x00,0xa0,0xc1,0x4c = ld1 {v0.16b, v1.16b}, [x0], x1
11 0xef,0xa5,0xc2,0x4c = ld1 {v1
[all...]

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