Searched refs:ldc1 (Results 1 - 25 of 48) sorted by relevance

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/external/llvm/test/MC/Mips/
H A Delf-relsym.s56 ldc1 $f0, %lo($CPI0_0)($2)
58 ldc1 $f2, 0($2)
60 ldc1 $f4, %lo($CPI0_1)($3)
64 ldc1 $f0, 0($1)
H A Dnacl-mask.s49 ldc1 $f2, 0($7)
84 # CHECK-NEXT: ldc1 $f2, 0($7)
H A Dmicromips-fpu-instructions.s21 # CHECK-EL: ldc1 $f2, 4($6) # encoding: [0x46,0xbc,0x04,0x00]
86 # CHECK-EB: ldc1 $f2, 4($6) # encoding: [0xbc,0x46,0x00,0x04]
149 ldc1 $f2, 4($6)
/external/v8/src/crankshaft/mips64/
H A Dlithium-gap-resolver-mips64.cc153 __ ldc1(kLithiumScratchDouble, cgen_->ToMemOperand(source));
214 __ ldc1(kLithiumScratchDouble, source_operand);
269 __ ldc1(cgen_->ToDoubleRegister(destination), source_operand);
285 __ ldc1(kLithiumScratchDouble, source_operand);
H A Dlithium-codegen-mips64.cc110 __ ldc1(DoubleRegister::from_code(save_iterator.Current()),
458 __ ldc1(dbl_scratch, mem_op);
2073 __ ldc1(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
2155 __ ldc1(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
2668 __ ldc1(result, FieldMemOperand(object, offset));
2812 __ ldc1(result, MemOperand(scratch0(), base_offset));
2898 __ ldc1(result, MemOperand(scratch));
4651 __ ldc1(result_reg, FieldMemOperand(input_reg, HeapNumber::kValueOffset));
4667 __ ldc1(result_reg, FieldMemOperand(scratch, HeapNumber::kValueOffset));
4716 __ ldc1(double_scratc
[all...]
/external/v8/src/crankshaft/mips/
H A Dlithium-gap-resolver-mips.cc153 __ ldc1(kLithiumScratchDouble, cgen_->ToMemOperand(source));
268 __ ldc1(cgen_->ToDoubleRegister(destination), source_operand);
284 __ ldc1(kLithiumScratchDouble, source_operand);
H A Dlithium-codegen-mips.cc134 __ ldc1(DoubleRegister::from_code(save_iterator.Current()),
475 __ ldc1(dbl_scratch, mem_op);
1952 __ ldc1(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
2034 __ ldc1(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
2546 __ ldc1(result, FieldMemOperand(object, offset));
2664 __ ldc1(result, MemOperand(scratch0(), base_offset));
2742 __ ldc1(result, MemOperand(scratch));
3867 __ ldc1(double_scratch,
4458 __ ldc1(result_reg, FieldMemOperand(input_reg, HeapNumber::kValueOffset));
4474 __ ldc1(result_re
[all...]
/external/valgrind/none/tests/mips64/
H A Dchange_fp_mode.stdout.exp6 ldc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
7 ldc1 $f1, 0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
55 ldc1 $f0, 0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
56 ldc1 $f1, 0($t0) :: lo32(f1): 12345678, lo32(f0): 90abcdef
104 ldc1 $f0, 0($t0) :: lo32(f1): 5a5a, lo32(f0): 90abcdef
105 ldc1 $f1, 0($t0) :: lo32(f1): 90abcdef, lo32(f0): 5a5a
/external/v8/src/mips/
H A Ddeoptimizer-mips.cc202 __ ldc1(f0, MemOperand(sp, src_offset));
273 __ ldc1(fpu_reg, MemOperand(a1, src_offset));
H A Dcode-stubs-mips.cc96 __ ldc1(double_scratch, MemOperand(input_reg, double_offset));
350 __ ldc1(f12, FieldMemOperand(lhs, HeapNumber::kValueOffset));
374 __ ldc1(f14, FieldMemOperand(rhs, HeapNumber::kValueOffset));
431 __ ldc1(f12, FieldMemOperand(lhs, HeapNumber::kValueOffset));
432 __ ldc1(f14, FieldMemOperand(rhs, HeapNumber::kValueOffset));
766 __ ldc1(double_exponent,
2141 __ ldc1(f2, MemOperand(a2, HeapNumber::kValueOffset));
2154 __ ldc1(f0, MemOperand(a2, HeapNumber::kValueOffset));
/external/v8/src/mips64/
H A Ddeoptimizer-mips64.cc202 __ ldc1(f0, MemOperand(sp, src_offset));
272 __ ldc1(fpu_reg, MemOperand(a1, src_offset));
H A Dcode-stubs-mips64.cc94 __ ldc1(double_scratch, MemOperand(input_reg, double_offset));
346 __ ldc1(f12, FieldMemOperand(lhs, HeapNumber::kValueOffset));
370 __ ldc1(f14, FieldMemOperand(rhs, HeapNumber::kValueOffset));
427 __ ldc1(f12, FieldMemOperand(lhs, HeapNumber::kValueOffset));
428 __ ldc1(f14, FieldMemOperand(rhs, HeapNumber::kValueOffset));
763 __ ldc1(double_exponent,
2148 __ ldc1(f2, MemOperand(a2, HeapNumber::kValueOffset));
2161 __ ldc1(f0, MemOperand(a2, HeapNumber::kValueOffset));
/external/llvm/test/MC/Mips/micromips32r6/
H A Dinvalid.s260 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
261 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
262 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
263 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
H A Dvalid.s357 ldc1 $f7, 300($10) # CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c]
358 ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
/external/llvm/test/MC/Mips/micromips64r6/
H A Dinvalid.s308 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
309 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
310 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
311 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
H A Dvalid.s310 ldc1 $f7, 300($10) # CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c]
311 ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c]
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s68 ldc1 $f11,16391($s0)
200 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s124 ldc1 $f11,16391($s0)
266 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s77 ldc1 $f11,16391($s0)
230 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s86 ldc1 $f11,16391($s0)
269 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s86 ldc1 $f11,16391($s0)
269 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s87 ldc1 $f11,16391($s0)
270 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s128 ldc1 $f11,16391($s0)
295 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s128 ldc1 $f11,16391($s0)
297 ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
/external/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.h195 void ldc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,

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