Searched refs:mfc1 (Results 1 - 25 of 39) sorted by relevance

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/external/valgrind/none/tests/mips32/
H A DMoveIns.stdout.exp2 mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
3 mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
4 mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
5 mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
6 mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
7 mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
8 mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
9 mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
10 mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
11 mfc1
[all...]
/external/valgrind/none/tests/mips64/
H A Dchange_fp_mode.stdout.exp22 mfc1 $t0, $f0 :: t0: ffffffff90abcdef
23 mfc1 $t0, $f1 :: t0: 5a5a
71 mfc1 $t0, $f0 :: t0: ffffffff90abcdef
72 mfc1 $t0, $f1 :: t0: 12345678
120 mfc1 $t0, $f0 :: t0: ffffffff90abcdef
121 mfc1 $t0, $f1 :: t0: 5a5a
/external/llvm/test/MC/Mips/
H A Dmicromips-fpu-instructions.s54 # CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
119 # CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
180 mfc1 $6, $f8
H A Dmips-fpu-instructions.s146 # CHECK: mfc1 $6, $f7 # encoding: [0x00,0x38,0x06,0x44]
181 mfc1 $a2,$f7
/external/v8/src/compiler/mips/
H A Dcode-generator-mips.cc493 __ mfc1(kScratchReg, i.InputDoubleRegister(0)); \
499 __ mfc1(at, i.OutputDoubleRegister()); \
1317 __ mfc1(i.OutputRegister(), scratch);
1323 __ mfc1(i.OutputRegister(), scratch);
1329 __ mfc1(i.OutputRegister(), scratch);
1336 __ mfc1(i.OutputRegister(), scratch);
1342 __ mfc1(i.OutputRegister(), scratch);
1348 __ mfc1(i.OutputRegister(), scratch);
1354 __ mfc1(i.OutputRegister(), scratch);
1360 __ mfc1(
[all...]
/external/v8/src/compiler/mips64/
H A Dcode-generator-mips64.cc530 __ mfc1(kScratchReg, i.InputDoubleRegister(0)); \
536 __ mfc1(at, i.OutputDoubleRegister()); \
1549 __ mfc1(i.OutputRegister(), scratch);
1555 __ mfc1(i.OutputRegister(), scratch);
1561 __ mfc1(i.OutputRegister(), scratch);
1568 __ mfc1(i.OutputRegister(), scratch);
1574 __ mfc1(i.OutputRegister(), scratch);
1580 __ mfc1(i.OutputRegister(), scratch);
1586 __ mfc1(i.OutputRegister(), scratch);
1592 __ mfc1(
[all...]
/external/capstone/suite/MC/Mips/
H A Dmips-fpu-instructions.s.cs62 0x00,0x38,0x06,0x44 = mfc1 $6, $f7
/external/v8/src/mips/
H A Dmacro-assembler-mips.cc1284 mfc1(scratch, fd);
1312 mfc1(scratch, fd);
1788 mfc1(scratch1, fs);
1937 mfc1(rs, scratch);
1945 mfc1(rs, scratch);
1967 mfc1(rs, scratch);
1975 mfc1(rs, scratch);
1993 mfc1(rt, fs.high());
2411 mfc1(result, double_scratch);
2448 mfc1(resul
[all...]
H A Ddisasm-mips.cc1340 Format(instr, "mfc1 'rt, 'fs");
H A Dmacro-assembler-mips.h282 mfc1(dst_low, src);
295 mfc1(dst_low, src);
/external/v8/src/mips64/
H A Dmacro-assembler-mips64.cc1476 mfc1(scratch, fd);
1838 mfc1(scratch1, fs);
1875 mfc1(t8, fs);
1928 mfc1(t8, fs);
2077 mfc1(rs, scratch);
2085 mfc1(rs, scratch);
2107 mfc1(rs, scratch);
2115 mfc1(rs, scratch);
2581 mfc1(result, double_scratch);
2618 mfc1(resul
[all...]
H A Dmacro-assembler-mips64.h311 mfc1(dst_low, src);
328 mfc1(dst_low, src);
/external/llvm/test/MC/Mips/mips1/
H A Dvalid.s62 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips2/
H A Dvalid.s82 mfc1 $a3,$f27
/external/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.h205 void mfc1(const Operand *OpRt, const Operand *OpFs);
H A DIceAssemblerMIPS32.cpp765 void AssemblerMIPS32::mfc1(const Operand *OpRt, const Operand *OpFs) { function in class:Ice::MIPS32::AssemblerMIPS32
767 emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mfc1");
804 mfc1(OpRd, OpRs);
/external/libjpeg-turbo/simd/
H A Djsimd_mips_dspr2.S2865 mfc1 t1, f2
2866 mfc1 t2, f4
2867 mfc1 t3, f6
2868 mfc1 t4, f8
2889 mfc1 t1, f2
2890 mfc1 t2, f4
2891 mfc1 t3, f6
2892 mfc1 t4, f8
/external/llvm/test/MC/Mips/micromips32r6/
H A Dvalid.s306 mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b]
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s140 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips32/
H A Dvalid.s94 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s108 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s108 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s109 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips4/
H A Dvalid.s148 mfc1 $a3,$f27
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s149 mfc1 $a3,$f27

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