| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 19 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 23 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 27 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 23 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/ |
| H A D | micromips-fpu-instructions.s | 56 # CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
121 # CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
182 mfhc1 $6, $f8
|
| H A D | mips-fpu-instructions.s | 172 # CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
207 mfhc1 $17, $f4
|
| H A D | target-soft-float.s | 38 mfhc1 $7, $f2
|
| /external/capstone/suite/MC/Mips/ |
| H A D | mips-fpu-instructions.s.cs | 88 0x00,0x20,0x71,0x44 = mfhc1 $17, $f4
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips32r2.s | 30 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/crankshaft/mips64/ |
| H A D | lithium-codegen-mips64.cc | 3462 __ mfhc1(scratch1, input); // Get exponent/sign bits.
3479 __ mfhc1(result, input);
3509 __ mfhc1(result, double_scratch0());
3510 // mfhc1 sign-extends, clear the upper bits.
3543 __ mfhc1(scratch, input); // Get exponent/sign bits.
4655 __ mfhc1(scratch, result_reg); // Get exponent/sign bits.
4734 __ mfhc1(scratch1, double_scratch); // Get exponent/sign bits.
4819 __ mfhc1(scratch1, double_input); // Get exponent/sign bits.
4854 __ mfhc1(scratch1, double_input); // Get exponent/sign bits.
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| H A D | valid.s | 310 mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 109 mfhc1 $s8,$f24
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | valid.s | 109 mfhc1 $s8,$f24
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | valid.s | 110 mfhc1 $s8,$f24
|
| /external/v8/src/mips/ |
| H A D | disasm-mips.cc | 1343 Format(instr, "mfhc1 'rt, 'fs");
|
| H A D | assembler-mips.cc | 2305 mfhc1(at, fd);
2311 mfhc1(t8, fd);
2333 void Assembler::mfhc1(Register rt, FPURegister fs) { function in class:v8::Assembler
|
| H A D | assembler-mips.h | 873 void mfhc1(Register rt, FPURegister fs);
|
| H A D | macro-assembler-mips.cc | 1997 mfhc1(rt, fs);
2252 mfhc1(at, dst);
|
| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.h | 312 mfhc1(dst_high, src);
320 mfhc1(dst_high, src);
|
| H A D | assembler-mips64.h | 930 void mfhc1(Register rt, FPURegister fs);
|
| H A D | assembler-mips64.cc | 2661 void Assembler::mfhc1(Register rt, FPURegister fs) { function in class:v8::internal::Assembler
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 177 mfhc1 $s8,$f24
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 177 mfhc1 $s8,$f24
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 178 mfhc1 $s8,$f24
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 503 __ mfhc1(kScratchReg, i.InputDoubleRegister(0)); \
|