Searched refs:mfhi (Results 1 - 25 of 41) sorted by relevance
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| /external/capstone/suite/MC/Mips/ |
| H A D | mips-dsp-instructions.s.cs | 30 0x00,0x20,0x70,0x10 = mfhi $14, $ac1
40 0x00,0x00,0x70,0x10 = mfhi $14
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| H A D | mips-fpu-instructions.s.cs | 63 0x10,0x28,0x00,0x00 = mfhi $5
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| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips1.s | 15 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips2.s | 21 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips1.s | 18 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips2.s | 24 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips3.s | 14 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| H A D | invalid-mips64.s | 23 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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| /external/llvm/test/MC/Mips/ |
| H A D | micromips-16-bit-instructions.s | 43 # CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
98 # CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
151 mfhi $9
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| H A D | mips-fpu-instructions.s | 147 # CHECK: mfhi $5 # encoding: [0x10,0x28,0x00,0x00]
182 mfhi $a1
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| /external/llvm/test/MC/Mips/dsp/ |
| H A D | valid.s | 57 mfhi $14, $ac1 # CHECK: mfhi $14, $ac1 # encoding: [0x00,0x20,0x70,0x10]
59 mfhi $14 # CHECK: mfhi $14 # encoding: [0x00,0x00,0x70,0x10]
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| /external/llvm/test/MC/Mips/dspr2/ |
| H A D | valid.s | 79 mfhi $14, $ac1 # CHECK: mfhi $14, $ac1 # encoding: [0x00,0x20,0x70,0x10]
81 mfhi $14 # CHECK: mfhi $14 # encoding: [0x00,0x00,0x70,0x10]
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| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 63 mfhi $s3
64 mfhi $sp
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| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 83 mfhi $s3
84 mfhi $sp
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| /external/llvm/test/MC/Mips/micromips-dsp/ |
| H A D | valid.s | 92 mfhi $2, $ac1 # CHECK: mfhi $2, $ac1 # encoding: [0x00,0x02,0x40,0x7c]
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| /external/libunwind_llvm/src/ |
| H A D | UnwindRegistersSave.S | 166 mfhi $8
222 mfhi $8
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| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 141 mfhi $s3
142 mfhi $sp
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| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 95 mfhi $s3
96 mfhi $sp
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| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 110 mfhi $s3
111 mfhi $sp
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| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | valid.s | 110 mfhi $s3
111 mfhi $sp
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| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | valid.s | 111 mfhi $s3
112 mfhi $sp
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| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 149 mfhi $s3
150 mfhi $sp
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| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 150 mfhi $s3
151 mfhi $sp
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| /external/v8/src/mips/ |
| H A D | macro-assembler-mips.cc | 606 mfhi(rd_hi);
626 mfhi(rd_hi);
656 mfhi(rd_hi);
675 mfhi(rd);
685 mfhi(rd);
709 mfhi(rd);
719 mfhi(rd);
757 mfhi(rem);
769 mfhi(rem);
804 mfhi(r
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerMIPS32.h | 207 void mfhi(const Operand *OpRd);
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