/external/llvm/test/MC/ARM/ |
H A D | elf-reloc-02.s | 17 movt r1, :upper16:.L.str
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H A D | target-expressions.s | 19 movt r0, :upper16:function 22 movt r1, #:upper16:function 25 movt r2, :upper16:deadbeat 28 movt r3, #:upper16:deadbeat 31 movt r4, :upper16:0xD1510D6E 34 movt r5, #:upper16:0xD1510D6E 37 movt r0, :upper16:external 40 movt r1, #:upper16:external 43 movt r2, #:upper16:(16 + 16) 46 movt r [all...] |
H A D | macho-movwt.s | 6 movt r0, :upper16:_x 9 movt r0, :upper16:_x+4 12 movt r0, :upper16:_x+0x10000 16 movt r0, :upper16:_x 19 movt r0, :upper16:_x+4 22 movt r0, :upper16:_x+0x10000
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H A D | thumb2be-movt-encoding.s | 4 movt r9, :upper16:(_bar) label 5 @ CHECK-LE: movt r9, :upper16:_bar @ encoding: [0xc0'A',0xf2'A',0b0000AAAA,0x09] 7 @ CHECK-BE: movt r9, :upper16:_bar @ encoding: [0xf2,0b1100AAAA,0x09'A',A]
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H A D | hilo-16bit-relocations.s | 6 movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8)) 10 @ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8))
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H A D | 2010-11-30-reloc-movt.s | 14 .file "/home/espindola/llvm/llvm/test/CodeGen/ARM/2010-11-30-reloc-movt.ll" 23 movt r0, :upper16:a
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H A D | thumb-movwt-reloc.s | 17 movt r0, :upper16:function 21 @ CHECK: movt r0, :upper16:function
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H A D | big-endian-thumb2-fixup.s | 17 movt r0, :upper16:GOT-(movt_label)
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H A D | arm_fixups.s | 14 movt r9, :upper16:(_foo) 24 @ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3] 26 @ CHECK-BE: movt r9, :upper16:_foo @ encoding: [0xe3,0b0100AAAA,0x90'A',A]
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H A D | elf-movt.s | 12 movt r0, :upper16:GOT-(.LPC0_2+8) 15 @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
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/external/capstone/suite/MC/Mips/ |
H A D | micromips-movcond-instructions-EB.s.cs | 4 0x55,0x26,0x09,0x7b = movt $9, $6, $fcc0
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H A D | micromips-movcond-instructions.s.cs | 4 0x26,0x55,0x7b,0x09 = movt $9, $6, $fcc0
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | hilo-16bit-relocations.s | 6 movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8)) 10 @ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8))
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H A D | thumb2-movt-fixup.s | 4 movt r3, :upper16:(_wilma-(LPC0_0+4))
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H A D | arm_fixups.s | 10 movt r9, :upper16:(_foo) 16 @ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3]
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H A D | elf-movt.s | 12 movt r0, :upper16:GOT-(.LPC0_2+8) 15 @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
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/external/valgrind/none/tests/mips32/ |
H A D | MoveIns.stdout.exp | 227 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1 228 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0 229 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1 230 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 231 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1 232 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0 233 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 234 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0 235 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 236 movt [all...] |
/external/llvm/test/MC/Mips/ |
H A D | micromips-movcond-instructions.s | 14 # CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09] 21 # CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b] 25 movt $9, $6, $fcc0
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/external/llvm/test/MC/Mips/mips3/ |
H A D | invalid-mips4.s | 21 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 22 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 23 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 24 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 25 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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H A D | invalid-mips5.s | 22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 23 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 26 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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/external/valgrind/coregrind/m_dispatch/ |
H A D | dispatch-arm-linux.S | 130 4 = movt r12, hi16(disp_cp_chain_me_to_slowEP) 145 4 = movt r12, hi16(disp_cp_chain_me_to_fastEP) 158 movt r1, #:upper16:vgPlain_stats__n_xindirs_32 169 movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast) 183 movt r1, #:upper16:vgPlain_stats__n_xindir_misses_32
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/external/llvm/test/ExecutionEngine/RuntimeDyld/ARM/ |
H A D | COFF_Thumb.s | 39 movt r0, :upper16:__imp_OutputDebugStringA 45 movt r0, :upper16:string 51 movt r0, :upper16:__imp_ExitProcess
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/external/llvm/test/MC/Mips/mips32r6/ |
H A D | invalid-mips32.s | 20 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 21 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 22 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/MachO/ARM/ |
H A D | thumb2-movw-fixup.s | 11 movt r2, :upper16:L1 13 movt r12, :upper16:L2
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/external/llvm/test/MC/ARM/Windows/ |
H A D | mov32t-range.s | 19 movt r0, :upper16:.Lerange
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