/external/llvm/test/MC/AArch64/ |
H A D | armv8.1a-vhe.s | 7 msr TTBR1_EL2, x0 8 msr CONTEXTIDR_EL2, x0 9 msr CNTHV_TVAL_EL2, x0 10 msr CNTHV_CVAL_EL2, x0 11 msr CNTHV_CTL_EL2, x0 12 msr SCTLR_EL12, x0 13 msr CPACR_EL12, x0 14 msr TTBR0_EL12, x0 15 msr TTBR1_EL12, x0 16 msr TCR_EL1 [all...] |
H A D | arm64-target-specific-sysreg.s | 7 msr CPM_IOACC_CTL_EL3, x0 label 10 // CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0 // encoding: [0x00,0xf2,0x1f,0xd5]
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H A D | armv8.2a-uao.s | 4 msr uao, #0 5 msr uao, #1 6 // CHECK: msr UAO, #0 // encoding: [0x7f,0x40,0x00,0xd5] 7 // CHECK: msr UAO, #1 // encoding: [0x7f,0x41,0x00,0xd5] 9 msr uao, #2 11 // CHECK-ERROR: msr uao, #2 14 msr uao, x1 16 // CHECK: msr UAO, x1 // encoding: [0x81,0x42,0x18,0xd5]
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H A D | trace-regs-diagnostics.s | 13 msr trcstatr, x0 14 msr trcidr8, x13 15 msr trcidr9, x25 16 msr trcidr10, x2 17 msr trcidr11, x19 18 msr trcidr12, x15 19 msr trcidr13, x24 20 msr trcidr0, x20 21 msr trcidr1, x5 22 msr trcidr [all...] |
H A D | armv8.1a-pan.s | 6 msr pan, #0 7 // CHECK: msr PAN, #0 // encoding: [0x9f,0x40,0x00,0xd5] 8 msr pan, #1 9 // CHECK: msr PAN, #1 // encoding: [0x9f,0x41,0x00,0xd5] 10 msr pan, x5 11 // CHECK: msr PAN, x5 // encoding: [0x65,0x42,0x18,0xd5] 15 msr pan, #-1 16 msr pan, #2 17 msr pan, w0 20 // CHECK-ERROR: msr pa [all...] |
H A D | arm64-spsel-sysreg.s | 4 msr SPSel, #0 label 5 msr SPSel, x0 label 6 msr DAIFSet, #0 label 7 msr ESR_EL1, x0 label 11 // CHECK: msr SPSel, #0 // encoding: [0xbf,0x40,0x00,0xd5] 12 // CHECK: msr SPSel, x0 // encoding: [0x00,0x42,0x18,0xd5] 13 // CHECK: msr DAIFSet, #0 // encoding: [0xdf,0x40,0x03,0xd5] 14 // CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5] 19 msr DAIFSet, x0 label 20 msr ESR_EL label [all...] |
H A D | gicv3-regs.s | 116 msr icc_eoir1_el1, x27 117 msr icc_eoir0_el1, x5 118 msr icc_dir_el1, x13 119 msr icc_sgi1r_el1, x21 120 msr icc_asgi1r_el1, x25 121 msr icc_sgi0r_el1, x28 122 msr icc_bpr1_el1, x7 123 msr icc_bpr0_el1, x9 124 msr icc_pmr_el1, x29 125 msr icc_ctlr_el [all...] |
H A D | armv8.2a-statistical-profiling.s | 8 msr pmblimitr_el1, x0 9 msr pmbptr_el1, x0 10 msr pmbsr_el1, x0 11 msr pmbidr_el1, x0 12 msr pmscr_el2, x0 13 msr pmscr_el12, x0 14 msr pmscr_el1, x0 15 msr pmsicr_el1, x0 16 msr pmsirr_el1, x0 17 msr pmsfcr_el [all...] |
H A D | ras-extension.s | 6 msr errselr_el1, x0 7 msr errselr_el1, x15 8 msr errselr_el1, x25 9 msr erxctlr_el1, x1 10 msr erxstatus_el1, x2 11 msr erxaddr_el1, x3 12 msr erxmisc0_el1, x4 13 msr erxmisc1_el1, x5 14 msr disr_el1, x6 15 msr vdisr_el [all...] |
H A D | trace-regs.s | 420 msr trcoslar, x28 421 msr trclar, x14 422 msr trcprgctlr, x10 423 msr trcprocselr, x27 424 msr trcconfigr, x24 425 msr trcauxctlr, x8 426 msr trceventctl0r, x16 427 msr trceventctl1r, x27 428 msr trcstallctlr, x26 429 msr trctsctl [all...] |
H A D | gicv3-regs-diagnostics.s | 30 msr icc_iar1_el1, x16 31 msr icc_iar0_el1, x19 32 msr icc_hppir1_el1, x29 33 msr icc_hppir0_el1, x14 34 msr icc_rpr_el1, x6 35 msr ich_vtr_el2, x8 36 msr ich_eisr_el2, x22 37 msr ich_elsr_el2, x8 39 // CHECK-NEXT: msr icc_iar1_el1, x16 42 // CHECK-NEXT: msr icc_iar0_el [all...] |
H A D | armv8.1a-lor.s | 25 msr LORSA_EL1, x0 26 msr LOREA_EL1, x0 27 msr LORN_EL1, x0 28 msr LORC_EL1, x0 30 // CHECK: msr LORSA_EL1, x0 // encoding: [0x00,0xa4,0x18,0xd5] 31 // CHECK: msr LOREA_EL1, x0 // encoding: [0x20,0xa4,0x18,0xd5] 32 // CHECK: msr LORN_EL1, x0 // encoding: [0x40,0xa4,0x18,0xd5] 33 // CHECK: msr LORC_EL1, x0 // encoding: [0x60,0xa4,0x18,0xd5] 41 msr LORSA_EL1, #0 42 msr LOREA_EL [all...] |
H A D | arm64-system-encoding.s | 60 msr ACTLR_EL1, x3 61 msr ACTLR_EL2, x3 62 msr ACTLR_EL3, x3 63 msr AFSR0_EL1, x3 64 msr AFSR0_EL2, x3 65 msr AFSR0_EL3, x3 66 msr AFSR1_EL1, x3 67 msr AFSR1_EL2, x3 68 msr AFSR1_EL3, x3 69 msr AMAIR_EL [all...] |
H A D | basic-a64-instructions.s | 3571 msr spsel, #0 3572 msr daifset, #15 3573 msr daifclr, #12 3574 // CHECK: msr {{SPSel|SPSEL}}, #0 // encoding: [0xbf,0x40,0x00,0xd5] 3575 // CHECK: msr {{DAIFSet|DAIFSET}}, #15 // encoding: [0xdf,0x4f,0x03,0xd5] 3576 // CHECK: msr {{DAIFClr|DAIFCLR}}, #12 // encoding: [0xff,0x4c,0x03,0xd5] 3702 msr TEECR32_EL1, x12 3703 msr OSDTRRX_EL1, x12 3704 msr MDCCINT_EL1, x12 3705 msr MDSCR_EL [all...] |
/external/capstone/suite/MC/ARM/ |
H A D | thumb2-mclass.s.cs | 16 0x80,0xf3,0x00,0x88 = msr apsr, r0 17 0x80,0xf3,0x00,0x88 = msr apsr, r0 18 0x80,0xf3,0x00,0x84 = msr apsr_g, r0 19 0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0 20 0x80,0xf3,0x01,0x88 = msr iapsr, r0 21 0x80,0xf3,0x01,0x88 = msr iapsr, r0 22 0x80,0xf3,0x01,0x84 = msr iapsr_g, r0 23 0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0 24 0x80,0xf3,0x02,0x88 = msr eapsr, r0 25 0x80,0xf3,0x02,0x88 = msr eaps [all...] |
/external/llvm/test/MC/ARM/ |
H A D | thumbv7em.s | 13 msr apsr_g, r0 14 msr apsr_nzcvqg, r0 15 msr iapsr_g, r0 16 msr iapsr_nzcvqg, r0 17 msr eapsr_g, r0 18 msr eapsr_nzcvqg, r0 19 msr xpsr_g, r0 20 msr xpsr_nzcvqg, r0 22 @ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] 23 @ CHECK: msr apsr_nzcvq [all...] |
H A D | thumb2-mclass.s | 41 msr apsr, r0 42 msr apsr_nzcvq, r0 43 msr iapsr, r0 44 msr iapsr_nzcvq, r0 45 msr eapsr, r0 46 msr eapsr_nzcvq, r0 47 msr xpsr, r0 48 msr xpsr_nzcvq, r0 49 msr ipsr, r0 50 msr eps [all...] |
H A D | move-banked-regs.s | 114 msr r8_usr, r2 115 msr r9_usr, r3 116 msr r10_usr, r5 117 msr r11_usr, r7 118 msr r12_usr, r11 119 msr sp_usr, r1 120 msr lr_usr, r2 121 @ CHECK-ARM: msr r8_usr, r2 @ encoding: [0x02,0xf2,0x20,0xe1] 122 @ CHECK-ARM: msr r9_usr, r3 @ encoding: [0x03,0xf2,0x21,0xe1] 123 @ CHECK-ARM: msr r10_us [all...] |
H A D | thumbv7m.s | 25 msr basepri, r0 26 msr basepri_max, r0 27 msr faultmask, r0 29 @ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88] 30 @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88] 31 @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88] 40 @ CHECK-V6M-NEXT: msr basepri, r0 42 @ CHECK-V6M-NEXT: msr basepri_max, r0 44 @ CHECK-V6M-NEXT: msr faultmask, r0
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/external/linux-kselftest/tools/testing/selftests/intel_pstate/ |
H A D | msr.c | 16 long long msr; local 28 sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu); 36 pread(fd, &msr, sizeof(msr), 0x199); 38 printf("msr 0x199: 0x%llx\n", msr);
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/external/strace/linux/powerpc64/ |
H A D | get_scno.c | 12 unsigned int currpers = (ppc_regs.msr & 0x8000000080000000) ? 0 : 1;
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/external/libgsm/src/ |
H A D | decode.c | 24 register word msr = S->msr; local 29 tmp = GSM_MULT_R( msr, 28180 ); 30 msr = GSM_ADD(*s, tmp); /* Deemphasis */ 31 *s = GSM_ADD(msr, msr) & 0xFFF8; /* Truncation & Upscaling */ 33 S->msr = msr;
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | thumb2-mclass.s | 46 msr apsr, r0
47 msr iapsr, r0
48 msr eapsr, r0
49 msr xpsr, r0
50 msr ipsr, r0
51 msr epsr, r0
52 msr iepsr, r0
53 msr msp, r0
54 msr psp, r0
55 msr primas [all...] |
/external/capstone/suite/MC/AArch64/ |
H A D | gicv3-regs.s.cs | 58 0x3b,0xcc,0x18,0xd5 = msr icc_eoir1_el1, x27 59 0x25,0xc8,0x18,0xd5 = msr icc_eoir0_el1, x5 60 0x2d,0xcb,0x18,0xd5 = msr icc_dir_el1, x13 61 0xb5,0xcb,0x18,0xd5 = msr icc_sgi1r_el1, x21 62 0xd9,0xcb,0x18,0xd5 = msr icc_asgi1r_el1, x25 63 0xfc,0xcb,0x18,0xd5 = msr icc_sgi0r_el1, x28 64 0x67,0xcc,0x18,0xd5 = msr icc_bpr1_el1, x7 65 0x69,0xc8,0x18,0xd5 = msr icc_bpr0_el1, x9 66 0x1d,0x46,0x18,0xd5 = msr icc_pmr_el1, x29 67 0x98,0xcc,0x18,0xd5 = msr icc_ctlr_el [all...] |
H A D | trace-regs.s.cs | 210 0x9c,0x10,0x11,0xd5 = msr trcoslar, x28 211 0xce,0x7c,0x11,0xd5 = msr trclar, x14 212 0x0a,0x01,0x11,0xd5 = msr trcprgctlr, x10 213 0x1b,0x02,0x11,0xd5 = msr trcprocselr, x27 214 0x18,0x04,0x11,0xd5 = msr trcconfigr, x24 215 0x08,0x06,0x11,0xd5 = msr trcauxctlr, x8 216 0x10,0x08,0x11,0xd5 = msr trceventctl0r, x16 217 0x1b,0x09,0x11,0xd5 = msr trceventctl1r, x27 218 0x1a,0x0b,0x11,0xd5 = msr trcstallctlr, x26 219 0x00,0x0c,0x11,0xd5 = msr trctsctl [all...] |