| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 22 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 27 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 31 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 24 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/ |
| H A D | micromips-fpu-instructions.s | 57 # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
122 # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
183 mthc1 $6, $f8
|
| H A D | mips-fpu-instructions.s | 173 # CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
208 mthc1 $17, $f6
|
| H A D | target-soft-float.s | 42 mthc1 $7, $f2
|
| /external/capstone/suite/MC/Mips/ |
| H A D | mips-fpu-instructions.s.cs | 89 0x00,0x30,0xf1,0x44 = mthc1 $17, $f6
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips32r2.s | 53 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | valid.s | 199 mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| H A D | valid.s | 302 mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 135 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | valid.s | 135 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | valid.s | 136 mthc1 $zero,$f16
|
| /external/v8/src/mips/ |
| H A D | disasm-mips.cc | 1356 Format(instr, "mthc1 'rt, 'fs");
|
| H A D | assembler-mips.cc | 2257 mthc1(at, fd);
2262 mthc1(at, fd);
2323 void Assembler::mthc1(Register rt, FPURegister fs) { function in class:v8::Assembler
|
| H A D | assembler-mips.h | 870 void mthc1(Register rt, FPURegister fs);
|
| H A D | macro-assembler-mips.cc | 1986 mthc1(rt, fs);
2254 mthc1(at, dst);
|
| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.h | 324 mthc1(src_high, dst);
335 mthc1(src_high, dst);
|
| H A D | macro-assembler-mips64.cc | 2067 mthc1(at, scratch);
2465 mthc1(at, dst);
2507 mthc1(at, dst);
2510 mthc1(at, dst);
2514 mthc1(at, dst);
2517 mthc1(zero_reg, dst);
|
| H A D | assembler-mips64.h | 926 void mthc1(Register rt, FPURegister fs);
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 204 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 204 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 205 mthc1 $zero,$f16
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 198 __ mthc1(at, result_);
|