/external/v8/src/interpreter/ |
H A D | bytecode-pipeline.h | 146 INLINE(BytecodeNode(Bytecode bytecode, uint32_t operand0, argument 153 SetOperand(0, operand0); 156 INLINE(BytecodeNode(Bytecode bytecode, uint32_t operand0, uint32_t operand1, argument 163 SetOperand(0, operand0); 167 INLINE(BytecodeNode(Bytecode bytecode, uint32_t operand0, uint32_t operand1, argument 175 SetOperand(0, operand0); 180 INLINE(BytecodeNode(Bytecode bytecode, uint32_t operand0, uint32_t operand1, argument 188 SetOperand(0, operand0); 210 void update_operand0(uint32_t operand0) { SetOperand(0, operand0); } argument 283 INLINE(static BytecodeNode Create(BytecodeSourceInfo source_info, uint32_t operand0)) argument 293 INLINE(static BytecodeNode Create(BytecodeSourceInfo source_info, uint32_t operand0, uint32_t operand1)) argument 306 INLINE(static BytecodeNode Create(BytecodeSourceInfo source_info, uint32_t operand0, uint32_t operand1, uint32_t operand2)) argument 323 INLINE(static BytecodeNode Create(BytecodeSourceInfo source_info, uint32_t operand0, uint32_t operand1, uint32_t operand2, uint32_t operand3)) argument [all...] |
H A D | bytecode-register-optimizer.cc | 275 uint32_t operand0 = static_cast<uint32_t>(input.ToOperand()); local 277 BytecodeNode node = BytecodeNode::Mov(source_info, operand0, operand1);
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/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_tgsi_vgpu10.c | 738 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc). 743 VGPU10OperandToken0 operand0, 753 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 || 754 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) { 757 assert(operand0.selectionMode == 0); 762 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) { 802 operand0.indexDimension = indexDim; 803 operand0.index0Representation = index0Rep; 804 operand0.index1Representation = index1Rep; 806 return operand0; 742 setup_operand0_indexing(struct svga_shader_emitter_v10 *emit, VGPU10OperandToken0 operand0, unsigned file, boolean indirect, boolean index2D, unsigned tempArrayID) argument 820 VGPU10OperandToken0 operand0; local 860 VGPU10OperandToken0 operand0; local 983 VGPU10OperandToken0 operand0; local 1120 VGPU10OperandToken0 operand0; local 1148 VGPU10OperandToken0 operand0; local 1169 VGPU10OperandToken0 operand0; local 1999 emit_decl_instruction(struct svga_shader_emitter_v10 *emit, VGPU10OpcodeToken0 opcode0, VGPU10OperandToken0 operand0, VGPU10NameToken name_token, unsigned index, unsigned size) argument 2057 VGPU10OperandToken0 operand0; local 2118 VGPU10OperandToken0 operand0; local 2156 VGPU10OperandToken0 operand0; local 2825 VGPU10OperandToken0 operand0; local 2926 VGPU10OperandToken0 operand0; local 3032 VGPU10OperandToken0 operand0; local [all...] |
/external/tensorflow/tensorflow/compiler/xla/service/gpu/ |
H A D | while_transformer.cc | 72 ExprTree(HloOpcode opcode, const ExprTree& operand0) : opcode_(opcode) { argument 73 SetOperand(0, operand0); 75 ExprTree(HloOpcode opcode, int64 index0, const ExprTree& operand0) argument 77 SetOperand(index0, operand0); 79 ExprTree(HloOpcode opcode, int64 index0, const ExprTree& operand0, argument 82 SetOperand(index0, operand0); 85 ExprTree(HloOpcode opcode, const string& tag, const ExprTree& operand0) argument 87 SetOperand(0, operand0); 89 ExprTree(HloOpcode opcode, const ExprTree& operand0, const ExprTree& operand1) argument 91 SetOperand(0, operand0); [all...] |
H A D | fusion_merger_test.cc | 294 auto* operand0 = root->operand(0); local 295 EXPECT_EQ(HloOpcode::kFusion, operand0->opcode()); 296 EXPECT_EQ(4, operand0->fused_instruction_count());
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/external/tensorflow/tensorflow/compiler/xla/service/ |
H A D | hlo_graph_dumper.cc | 249 const HloInstruction* operand0 = root->operand(0); local 251 if (operand0->opcode() != HloOpcode::kParameter || 258 auto n0 = operand0->parameter_number(); 280 !ShapeUtil::IsEffectiveScalar(operand0->shape()) ||
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/external/v8/src/compiler/ia32/ |
H A D | instruction-selector-ia32.cc | 187 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); local 190 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); 192 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1);
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/external/v8/src/compiler/x64/ |
H A D | instruction-selector-x64.cc | 1277 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); local 1280 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); 1282 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1);
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/external/annotation-tools/asmx/test/lib/ |
H A D | saxon7.jar | META-INF/ META-INF/MANIFEST.MF net/sf/saxon/Compile.class Compile.java package ... |