Searched refs:reg1 (Results 1 - 25 of 84) sorted by relevance

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/external/libvpx/libvpx/vpx_ports/
H A Dasmdefs_mmi.h21 #define MMI_ADDU(reg1, reg2, reg3) \
22 "daddu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
24 #define MMI_ADDIU(reg1, reg2, immediate) \
25 "daddiu " #reg1 ", " #reg2 ", " #immediate " \n\t"
27 #define MMI_ADDI(reg1, reg2, immediate) \
28 "daddi " #reg1 ", " #reg2 ", " #immediate " \n\t"
30 #define MMI_SUBU(reg1, reg2, reg3) \
31 "dsubu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
36 #define MMI_SRL(reg1, reg2, shift) \
37 "dsrl " #reg1 ", " #reg
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/external/libavc/common/armv8/
H A Dih264_neon_macros.s36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
/external/libmpeg2/common/armv8/
H A Dimpeg2_neon_macros.s53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
/external/llvm/test/MC/MachO/
H A Dbad-macro.s5 .macro test_macro reg1, reg2
/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7);
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1);
75 reg2 = reg1 + reg5;
76 reg1
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
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H A Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1,
40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15);
43 reg9 = reg1 - loc2;
44 reg1 = reg1 + loc2;
57 loc1 = reg1
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
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H A Dtxfm_macros_msa.h16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
27 ILVRL_H2_SW(reg1, reg0, s5_m, s4_m); \
28 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
/external/libunwind/src/ptrace/
H A D_UPT_access_mem.c63 long reg1, reg2;
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0);
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
/external/capstone/arch/X86/
H A DX86Mapping.h36 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, x86_reg *reg2);
37 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2);
/external/webrtc/webrtc/system_wrappers/include/
H A Dasm_defines.h59 .macro streqh reg1, reg2, num
60 strheq \reg1, \reg2, \num variable
/external/boringssl/src/crypto/perlasm/
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
/external/libyuv/files/source/
H A Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; local
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11);
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1);
570 v8u16 reg0, reg1, reg2; local
586 reg1 = (v8u16)__msa_srai_h(vec1, 4);
588 reg1 = (v8u16)__msa_slli_h((v8i16)reg1, 4);
590 reg1 |= const_0xF000;
592 dst0 = (v16u8)(reg1 | reg0);
610 v8u16 reg0, reg1, reg local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1159 v4u32 reg0, reg1, reg2, reg3; local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
1305 v8i16 reg0, reg1, reg2; local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local
1433 v8u16 reg0, reg1, reg2; local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
2020 v8i16 reg0, reg1, reg2, reg3; local
2125 v8i16 reg0, reg1, reg2, reg3; local
2385 v16u8 reg0, reg1, dst0, dst1, dst2, dst3; local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
2729 v4i32 reg0, reg1, reg2, reg3; local
[all...]
H A Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3);
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1);
138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1);
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3);
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg
[all...]
H A Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; local
83 reg1 = __msa_hadd_u_h(vec1, vec1);
87 reg1 += reg3;
89 reg1 = (v8u16)__msa_srari_h((v8i16)reg1, 2);
90 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0);
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
158 reg1 = __msa_hadd_u_h(vec1, vec1);
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1);
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1);
296 v4u32 reg0, reg1, reg2, reg3; local
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/external/v8/src/interpreter/
H A Dbytecode-register.cc107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, argument
109 if (reg1.index() + 1 != reg2.index()) {
H A Dbytecode-register.h65 static bool AreContiguous(Register reg1, Register reg2,
/external/mesa3d/src/util/
H A Dregister_allocate.c234 struct ra_reg *reg1 = &regs->regs[r1]; local
236 if (reg1->conflict_list) {
237 if (reg1->conflict_list_size == reg1->num_conflicts) {
238 reg1->conflict_list_size *= 2;
239 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
240 unsigned int, reg1->conflict_list_size);
242 reg1->conflict_list[reg1
[all...]
/external/v8/src/compiler/mips64/
H A Dcode-generator-mips64.cc1040 Register reg1 = kScratchReg; local
1051 __ li(reg1, 0x1F);
1052 __ Subu(i.OutputRegister(), reg1, reg2);
1060 Register reg1 = kScratchReg; local
1071 __ li(reg1, 0x3F);
1072 __ Subu(i.OutputRegister(), reg1, reg2);
1080 Register reg1 = kScratchReg; local
1090 __ dsrl(reg1, i.InputRegister(0), 1);
1092 __ And(reg1, reg1, a
1124 Register reg1 = kScratchReg; local
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/external/aac/libFDK/include/
H A Dfixpoint_math.h296 FIXP_DBL reg1, reg2; local
319 reg1 = invSqrtTab[index] + (fMultDiv2(diff, Fract) << 1);
321 /* reg1 = t[i] + (t[i+1]-t[i])*fract ... already computed ...
327 reg1 = fMultAddDiv2(reg1, Fract, diff);
341 reg1 = fMultDiv2(reg1, reg2) << 2;
346 return (reg1);
/external/vixl/src/aarch64/
H A Doperands-aarch64.h474 bool AreAliased(const CPURegister& reg1,
487 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
488 bool AreSameSizeAndType(const CPURegister& reg1,
500 // arguments. At least one argument (reg1) must be valid (not NoVReg).
501 bool AreSameFormat(const VRegister& reg1,
509 // any subsequent arguments. At least one argument (reg1) must be valid
511 bool AreConsecutive(const VRegister& reg1,
520 explicit CPURegList(CPURegister reg1,
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
525 size_(reg1
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/external/v8/src/compiler/mips/
H A Dcode-generator-mips.cc916 Register reg1 = kScratchReg; local
927 __ li(reg1, 0x1F);
928 __ Subu(i.OutputRegister(), reg1, reg2);
936 Register reg1 = kScratchReg; local
946 __ srl(reg1, i.InputRegister(0), 1);
948 __ And(reg1, reg1, at);
949 __ addu(reg1, reg1, reg2);
953 __ srl(reg2, reg1,
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp150 bool haveSameParity(unsigned reg1, unsigned reg2) { argument
151 assert(isFPReg(reg1) && "Expecting an FP register for reg1");
154 return isOdd(reg1) == isOdd(reg2);
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.h463 RegisterList(Register reg1, Register reg2)
464 : list_(RegisterToList(reg1) | RegisterToList(reg2)) {}
465 RegisterList(Register reg1, Register reg2, Register reg3)
466 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
468 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
469 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
552 VRegisterList(VRegister reg1, VRegister reg2)
553 : list_(RegisterToList(reg1) | RegisterToList(reg2)) {}
554 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3)
555 : list_(RegisterToList(reg1) | RegisterToLis
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