Searched refs:reg2 (Results 1 - 25 of 84) sorted by relevance

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/external/libvpx/libvpx/vpx_ports/
H A Dasmdefs_mmi.h21 #define MMI_ADDU(reg1, reg2, reg3) \
22 "daddu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
24 #define MMI_ADDIU(reg1, reg2, immediate) \
25 "daddiu " #reg1 ", " #reg2 ", " #immediate " \n\t"
27 #define MMI_ADDI(reg1, reg2, immediate) \
28 "daddi " #reg1 ", " #reg2 ", " #immediate " \n\t"
30 #define MMI_SUBU(reg1, reg2, reg3) \
31 "dsubu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
36 #define MMI_SRL(reg1, reg2, shift) \
37 "dsrl " #reg1 ", " #reg2 ", " #shif
[all...]
/external/libavc/common/armv8/
H A Dih264_neon_macros.s36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
/external/libmpeg2/common/armv8/
H A Dimpeg2_neon_macros.s53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
/external/llvm/test/MC/MachO/
H A Dbad-macro.s5 .macro test_macro reg1, reg2
/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
59 DOTP_CONST_PAIR(reg2, reg6, cospi_24_64, cospi_8_64, reg2, reg6);
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
68 DOTP_CONST_PAIR(reg2, reg5, cospi_22_64, cospi_10_64, reg2, reg5);
73 reg4 = reg6 + reg2;
74 reg6 = reg6 - reg2;
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
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H A Didct16x16_msa.c15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1,
24 reg2, reg3, reg4, reg5, reg6, reg7);
27 DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14);
29 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2);
30 DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3);
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
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/external/libunwind/src/ptrace/
H A D_UPT_access_mem.c63 long reg1, reg2;
67 reg2 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) (addr + sizeof(long)), 0);
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
/external/capstone/arch/X86/
H A DX86Mapping.h36 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, x86_reg *reg2);
37 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2);
/external/webrtc/webrtc/system_wrappers/include/
H A Dasm_defines.h59 .macro streqh reg1, reg2, num variable
60 strheq \reg1, \reg2, \num variable
/external/boringssl/src/crypto/perlasm/
H A Dx86masm.pl46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
65 if ($reg2 ne "")
67 $ret .= "$reg2*$idx";
H A Dx86nasm.pl43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
66 if ($reg2 ne "")
68 $ret .= "$reg2*$idx";
H A Dx86gas.pl77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
87 $reg2 = "%$reg2" if ($reg2);
91 if ($reg2)
93 $ret .= "($reg1,$reg2,$idx)";
/external/v8/src/interpreter/
H A Dbytecode-register.cc107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, argument
109 if (reg1.index() + 1 != reg2.index()) {
112 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) {
H A Dbytecode-register.h65 static bool AreContiguous(Register reg1, Register reg2,
/external/libyuv/files/source/
H A Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; local
507 reg2 = (v16u8)__msa_ilvev_b((v16i8)vec4, (v16i8)vec3);
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11);
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2);
570 v8u16 reg0, reg1, reg2; local
587 reg2 = (v8u16)__msa_srai_h(vec2, 4);
589 reg2 = (v8u16)__msa_slli_h((v8i16)reg2, 8);
591 reg0 |= reg2;
610 v8u16 reg0, reg1, reg2; local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1159 v4u32 reg0, reg1, reg2, reg3; local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
1305 v8i16 reg0, reg1, reg2; local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local
1433 v8u16 reg0, reg1, reg2; local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
2020 v8i16 reg0, reg1, reg2, reg3; local
2125 v8i16 reg0, reg1, reg2, reg3; local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
2729 v4i32 reg0, reg1, reg2, reg3; local
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H A Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
142 res8 = (v16u8)__msa_ilvr_w((v4i32)reg6, (v4i32)reg2);
143 res9 = (v16u8)__msa_ilvl_w((v4i32)reg6, (v4i32)reg2);
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg
[all...]
H A Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; local
84 reg2 = __msa_hadd_u_h(vec2, vec2);
86 reg0 += reg2;
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
159 reg2 = __msa_hadd_u_h(vec2, vec2);
161 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0);
163 reg6 = (v8u16)__msa_pckod_d((v2i64)reg2, (v2i64)reg0);
296 v4u32 reg0, reg1, reg2, reg3; local
333 reg2 = __msa_hadd_u_w(vec2, vec2);
337 reg2
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/external/v8/src/compiler/mips64/
H A Dcode-generator-mips64.cc1041 Register reg2 = kScratchReg2; local
1047 __ Subu(reg2, zero_reg, i.InputRegister(0));
1048 __ And(reg2, reg2, i.InputRegister(0));
1049 __ clz(reg2, reg2);
1052 __ Subu(i.OutputRegister(), reg1, reg2);
1061 Register reg2 = kScratchReg2; local
1067 __ Dsubu(reg2, zero_reg, i.InputRegister(0));
1068 __ And(reg2, reg
1081 Register reg2 = kScratchReg2; local
1125 Register reg2 = kScratchReg2; local
[all...]
/external/valgrind/none/tests/s390x/
H A Dcksm.c26 register uint64_t reg2 asm("2") = (uint64_t) buff;
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
37 addr = reg2;
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3_sched.c630 struct ir3_register *reg, *reg2; local
636 foreach_src(reg2, instr) {
637 if (reg == reg2)
639 /* reg2 is before reg1 so already an inserted mov: */
640 else if (reg2->instr->regs[1]->instr == src) {
641 mov = reg2->instr;
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_fragshader.c49 GLuint reg2 = 0; local
54 reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
59 reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
65 reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos));
80 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT;
85 reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT;
109 SET_INST_2(opnum, optype) |= reg2;
/external/vixl/src/aarch64/
H A Doperands-aarch64.h475 const CPURegister& reg2,
489 const CPURegister& reg2,
502 const VRegister& reg2,
512 const VRegister& reg2,
521 CPURegister reg2 = NoCPUReg,
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
527 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
/external/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp150 bool haveSameParity(unsigned reg1, unsigned reg2) { argument
152 assert(isFPReg(reg2) && "Expecting an FP register for reg2");
154 return isOdd(reg1) == isOdd(reg2);
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.h463 RegisterList(Register reg1, Register reg2)
464 : list_(RegisterToList(reg1) | RegisterToList(reg2)) {}
465 RegisterList(Register reg1, Register reg2, Register reg3)
466 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
468 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
469 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
552 VRegisterList(VRegister reg1, VRegister reg2)
553 : list_(RegisterToList(reg1) | RegisterToList(reg2)) {}
554 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3)
555 : list_(RegisterToList(reg1) | RegisterToList(reg2) |
[all...]
/external/v8/src/compiler/mips/
H A Dcode-generator-mips.cc917 Register reg2 = kScratchReg2; local
923 __ Subu(reg2, zero_reg, i.InputRegister(0));
924 __ And(reg2, reg2, i.InputRegister(0));
925 __ clz(reg2, reg2);
928 __ Subu(i.OutputRegister(), reg1, reg2);
937 Register reg2 = kScratchReg2; local
947 __ And(reg2, i.InputRegister(0), at);
949 __ addu(reg1, reg1, reg2);
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