| /external/llvm/test/MC/Mips/mips32/ |
| H A D | invalid-mips32r2.s | 32 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips64r2.s | 30 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | invalid-mips64r2.s | 37 seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | invalid-mips64r2.s | 29 seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips32r2.s | 64 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| H A D | valid.s | 108 seb $3, $4 # CHECK: seb $3, $4 # encoding: [0x00,0x64,0x2b,0x3c]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 178 seb $25,$15
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | valid.s | 178 seb $25,$15
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | valid.s | 179 seb $25,$15
|
| /external/v8/src/mips/ |
| H A D | disasm-mips.cc | 1285 Format(instr, "seb 'rd, 'rt");
|
| H A D | assembler-mips.h | 858 void seb(Register rd, Register rt);
|
| H A D | assembler-mips.cc | 2212 void Assembler::seb(Register rd, Register rt) { function in class:v8::Assembler
|
| H A D | macro-assembler-mips.cc | 1754 seb(rd, rt);
|
| /external/llvm/test/MC/SystemZ/ |
| H A D | insn-bad.s | 2977 #CHECK: seb %f0, -1
2979 #CHECK: seb %f0, 4096
2981 seb %f0, -1
2982 seb %f0, 4096
|
| H A D | insn-good.s | 8434 #CHECK: seb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0b]
8435 #CHECK: seb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0b]
8436 #CHECK: seb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0b]
8437 #CHECK: seb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0b]
8438 #CHECK: seb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0b]
8439 #CHECK: seb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0b]
8440 #CHECK: seb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0b]
8442 seb %f0, 0
8443 seb %f0, 4095
8444 seb
[all...] |
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 251 seb $25,$15
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 251 seb $25,$15
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 252 seb $25,$15
|
| /external/capstone/suite/MC/SystemZ/ |
| H A D | insn-good.s.cs | 1788 0xed,0x00,0x00,0x00,0x00,0x0b = seb %f0, 0
1789 0xed,0x00,0x0f,0xff,0x00,0x0b = seb %f0, 4095
1790 0xed,0x00,0x10,0x00,0x00,0x0b = seb %f0, 0(%r1)
1791 0xed,0x00,0xf0,0x00,0x00,0x0b = seb %f0, 0(%r15)
1792 0xed,0x01,0xff,0xff,0x00,0x0b = seb %f0, 4095(%r1,%r15)
1793 0xed,0x0f,0x1f,0xff,0x00,0x0b = seb %f0, 4095(%r15,%r1)
1794 0xed,0xf0,0x00,0x00,0x00,0x0b = seb %f15, 0
|
| /external/v8/src/mips64/ |
| H A D | assembler-mips64.h | 914 void seb(Register rd, Register rt);
|
| H A D | assembler-mips64.cc | 2592 void Assembler::seb(Register rd, Register rt) { function in class:v8::internal::Assembler
|
| H A D | macro-assembler-mips64.cc | 1209 seb(src, src);
|
| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1709 __ seb(i.OutputRegister(), i.InputRegister(0));
|
| /external/v8/src/s390/ |
| H A D | constants-s390.h | 232 V(seb, SEB, 0xED0B) /* type = RXE SUBTRACT (short BFP) */ \
|