| /external/llvm/test/MC/Mips/ |
| H A D | rotations32.s | 24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl
[all...] |
| H A D | micromips-shift-instructions.s | 14 # CHECK-EL: srl $4, $3, 7 # encoding: [0x83,0x00,0x40,0x38]
26 # CHECK-EL: srl $3, $3, 7 # encoding: [0x63,0x00,0x40,0x38]
34 # CHECK-EB: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
46 # CHECK-EB: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
51 srl $4, $3, 7
57 srl $2, $3, $5
60 srl $2, $3
63 srl $3, 7
|
| H A D | rotations64.s | 24 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-64: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-64: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-64: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-64: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-64: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-64: srl
[all...] |
| H A D | mips-alu-instructions.s | 30 # CHECK: srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
61 srl $4, $3, 7
|
| H A D | mips64-alu-instructions.s | 28 # CHECK: srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
56 srl $4, $3, 7
|
| /external/capstone/suite/MC/Mips/ |
| H A D | micromips-shift-instructions-EB.s.cs | 6 0x00,0x83,0x38,0x40 = srl $4, $3, 7
|
| H A D | micromips-shift-instructions.s.cs | 6 0x83,0x00,0x40,0x38 = srl $4, $3, 7
|
| H A D | mips-alu-instructions.s.cs | 25 0xc2,0x21,0x03,0x00 = srl $4, $3, 7
|
| H A D | mips64-alu-instructions.s.cs | 23 0xc2,0x21,0x03,0x00 = srl $4, $3, 7
|
| /external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
| H A D | mblaze_shift.s | 44 # CHECK: srl
47 srl r1, r2
|
| /external/icu/icu4c/source/config/ |
| H A D | test-icu-config.sh | 48 icu-config --prefix=/Users/srl/II --cflags
|
| /external/valgrind/coregrind/m_dispatch/ |
| H A D | dispatch-mips32-linux.S | 190 srl $14, $14, 2
|
| H A D | dispatch-mips64-linux.S | 190 srl $14, $14, 2
|
| /external/libffi/src/mips/ |
| H A D | ffitarget.h | 152 # define SRL srl
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
| H A D | ffitarget.h | 152 # define SRL srl
|
| /external/python/cpython3/Modules/_ctypes/libffi/src/mips/ |
| H A D | ffitarget.h | 152 # define SRL srl
|
| /external/capstone/suite/MC/Sparc/ |
| H A D | sparc-alu-instructions.s.cs | 22 0x87,0x30,0x40,0x02 = srl %g1, %g2, %g3
23 0x87,0x30,0x60,0x1f = srl %g1, 31, %g3
|
| /external/icu/icu4c/packaging/rpm/ |
| H A D | icu.spec | 220 * Tue Aug 16 2003 Steven Loomis <srl@jtcsv.com>
222 * Thu Jun 05 2003 Steven Loomis <srl@jtcsv.com>
224 * Fri Dec 27 2002 Steven Loomis <srl@jtcsv.com>
226 * Fri Sep 27 2002 Steven Loomis <srl@jtcsv.com>
|
| /external/llvm/test/MC/Sparc/ |
| H A D | sparc-alu-instructions.s | 55 ! CHECK: srl %g1, %g2, %g3 ! encoding: [0x87,0x30,0x40,0x02]
56 srl %g1, %g2, %g3
57 ! CHECK: srl %g1, 31, %g3 ! encoding: [0x87,0x30,0x60,0x1f]
58 srl %g1, 31, %g3
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | valid.s | 103 srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
104 srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
105 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 131 srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
132 srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
133 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/libjpeg-turbo/simd/ |
| H A D | jsimd_mips_dspr2.S | 570 srl t3, a0, 1
774 srl t0, a0, 1
896 srl t4, s5, 1
917 srl t1, t1, 4
939 srl t6, t0, 16 // t6 = next2
943 srl t0, t0, 4 // t0 = (this*3 + next1 + 7) >> 4
947 srl t2, t2, 4 // t2 = (next1*3 + next2 + 7) >> 4
971 srl t0, t0, 4
985 srl t0, t0, 4
992 srl t
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 196 srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
197 srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
198 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 161 srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
162 srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
163 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 196 srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
197 srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
198 srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
|