/external/libffi/src/m88k/ |
H A D | obsd.S | 58 subu %r31, %r31, 32 71 subu %r31, %r31, %r2 85 subu %r4, %r30, 32 99 subu %r31, %r30, 32 131 subu %r31, %r31, 16 138 subu %r31, %r31, (8 * 4) + (2 * 4) 167 subu %r31, %r30, 16 181 subu %r31, %r31, 16 187 subu %r31, %r31, (8 * 4) 204 subu [all...] |
/external/python/cpython2/Modules/_ctypes/libffi/src/m88k/ |
H A D | obsd.S | 58 subu %r31, %r31, 32 71 subu %r31, %r31, %r2 85 subu %r4, %r30, 32 99 subu %r31, %r30, 32 131 subu %r31, %r31, 16 138 subu %r31, %r31, (8 * 4) + (2 * 4) 167 subu %r31, %r30, 16 181 subu %r31, %r31, 16 187 subu %r31, %r31, (8 * 4) 204 subu [all...] |
/external/python/cpython3/Modules/_ctypes/libffi/src/m88k/ |
H A D | obsd.S | 58 subu %r31, %r31, 32 71 subu %r31, %r31, %r2 85 subu %r4, %r30, 32 99 subu %r31, %r30, 32 131 subu %r31, %r31, 16 138 subu %r31, %r31, (8 * 4) + (2 * 4) 167 subu %r31, %r30, 16 181 subu %r31, %r31, 16 187 subu %r31, %r31, (8 * 4) 204 subu [all...] |
/external/libjpeg-turbo/simd/ |
H A D | jsimd_mips_dspr2.S | 319 subu.ph t2, t2, t8 322 subu t0, 128 405 subu t8, t9, t7 913 subu t1, t0, t7 // t1 = thiscolsum * 3 980 subu t1, t0, t6 // t1 = thiscolsum * 3 993 subu t0, a0, t0 1136 subu s2, t7, s2 1237 subu s2, t7, s2 1340 subu v0, v0, s0 1365 subu t [all...] |
/external/llvm/test/MC/Mips/ |
H A D | mips-alu-instructions.s | 90 # CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00] 115 subu $4,$3,$5 116 subu $sp,$sp,40 134 # CHECK: subu $9, $9, $3 # encoding: [0x23,0x48,0x23,0x01] 146 subu $9, $3 148 subu $9, 10
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H A D | micromips-alu-instructions.s | 17 # CHECK-EL: subu $4, $3, $5 # encoding: [0xa3,0x00,0xd0,0x21] 60 # CHECK-EB: subu $4, $3, $5 # encoding: [0x00,0xa3,0x21,0xd0] 100 subu $4, $3, $5
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H A D | rotations64.s | 10 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23] 14 # CHECK-64R: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23] 17 # CHECK-64: subu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x23] 51 # CHECK-64: subu $1, $zero, $5 # encoding: [0x00,0x05,0x08,0x23] 57 # CHECK-64: subu $1, $zero, $6 # encoding: [0x00,0x06,0x08,0x23]
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/external/valgrind/coregrind/m_syswrap/ |
H A D | syscall-mips32-linux.S | 81 subu $29, $29, 56 #set up the steck frame, 120 subu $29, $29, 24 #set up the steck frame,
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/external/capstone/suite/MC/Mips/ |
H A D | micromips-alu-instructions-EB.s.cs | 9 0x00,0xa3,0x21,0xd0 = subu $4, $3, $5
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H A D | micromips-alu-instructions.s.cs | 9 0xa3,0x00,0xd0,0x21 = subu $4, $3, $5
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H A D | mips-alu-instructions.s.cs | 49 0x23,0x20,0x65,0x00 = subu $4, $3, $5
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/external/libffi/src/mips/ |
H A D | ffitarget.h | 150 # define SUBU subu
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/external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
H A D | ffitarget.h | 150 # define SUBU subu
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/external/python/cpython3/Modules/_ctypes/libffi/src/mips/ |
H A D | ffitarget.h | 150 # define SUBU subu
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/external/v8/src/mips/ |
H A D | codegen-mips.cc | 80 __ subu(a3, zero_reg, a0); // In delay slot. 84 __ subu(a2, a2, a3); // In delay slot. a2 is the remining bytes count. 104 __ subu(a3, a2, t8); // In delay slot. 215 __ subu(a3, t8, a2); // In delay slot. 246 __ subu(a2, a2, a3); // In delay slot. 271 __ subu(a3, a2, t8); // In delay slot. 512 __ subu(a3, t8, a2); // In delay slot.
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/external/v8/src/mips64/ |
H A D | codegen-mips64.cc | 80 __ subu(a3, zero_reg, a0); // In delay slot. 84 __ subu(a2, a2, a3); // In delay slot. a2 is the remining bytes count. 105 __ subu(a3, a2, t8); // In delay slot. 216 __ subu(a3, t8, a2); // In delay slot. 247 __ subu(a2, a2, a3); // In delay slot. 272 __ subu(a3, a2, t8); // In delay slot. 514 __ subu(a3, t8, a2); // In delay slot.
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/external/llvm/test/MC/Mips/micromips-dspr2/ |
H A D | valid.s | 100 subu.ph $3, $4, $5 # CHECK: subu.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x0d] 102 subu.qb $3, $4, $5 # CHECK: subu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xcd]
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/external/llvm/test/MC/Mips/dspr2/ |
H A D | valid.s | 170 subu.ph $6, $2, $9 # CHECK: subu.ph $6, $2, $9 # encoding: [0x7c,0x49,0x32,0x50] 172 subu.qb $1, $2, $3 # CHECK: subu.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0x50]
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/external/llvm/test/MC/Mips/micromips-dsp/ |
H A D | valid.s | 74 subu.qb $3, $4, $5 # CHECK: subu.qb $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xcd]
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/external/llvm/test/MC/Mips/dsp/ |
H A D | valid.s | 126 subu.qb $1, $2, $3 # CHECK: subu.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0x50]
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/external/valgrind/none/tests/mips32/ |
H A D | mips32_dspr2.stdout.exp | 2073 subu.ph $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 2074 subu.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 2075 subu.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 2076 subu.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941fcbfc DSPCtrl 0x00100000 2077 subu.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 2078 subu.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0002 DSPCtrl 0x00100000 2079 subu.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f005 DSPCtrl 0x00100000 2080 subu.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 2081 subu.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 2082 subu [all...] |
/external/llvm/test/MC/Mips/mips1/ |
H A D | valid.s | 113 subu $sp,$s6,$s6
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/external/llvm/test/MC/Mips/mips2/ |
H A D | valid.s | 141 subu $sp,$s6,$s6
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/external/llvm/test/MC/Mips/mips32r2/ |
H A D | invalid-dspr2.s | 129 subu.ph $9,$s6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 130 subu.qb $s6,$a2,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerMIPS32.h | 287 void subu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
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