| /external/capstone/suite/MC/Mips/ |
| H A D | micromips-trap-instructions-EB.s.cs | 5 0x01,0x28,0x08,0x3c = tlt $8, $9
|
| H A D | micromips-trap-instructions.s.cs | 5 0x28,0x01,0x3c,0x08 = tlt $8, $9
|
| H A D | mips-control-instructions-64.s.cs | 25 0x00,0x03,0x00,0x32 = tlt $zero, $3
26 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
|
| H A D | mips-control-instructions.s.cs | 25 0x00,0x03,0x00,0x32 = tlt $zero, $3
26 0x00,0x03,0x07,0xf2 = tlt $zero, $3, 31
|
| /external/llvm/test/MC/Mips/ |
| H A D | micromips-trap-instructions.s | 15 # CHECK-EL: tlt $8, $9 # encoding: [0x28,0x01,0x3c,0x08]
30 # CHECK-EB: tlt $8, $9 # encoding: [0x01,0x28,0x08,0x3c]
42 tlt $8, $9, 0
|
| H A D | mips-control-instructions.s | 27 # CHECK32: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
28 # CHECK32: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
58 # CHECK64: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
59 # CHECK64: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
92 tlt $0,$3
93 tlt $0,$3,31
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| H A D | invalid-wrong-error.s | 19 tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
20 tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
21 tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 261 tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
262 tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
|
| H A D | invalid.s | 65 tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
66 tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| H A D | invalid-wrong-error.s | 27 tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
28 tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
29 tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
|
| H A D | valid.s | 133 tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xaf,0x08,0x3c]
134 tlt $2, $19, 15 # CHECK: tlt $2, $19, 15 # encoding: [0x02,0x62,0xf8,0x3c]
|
| H A D | invalid.s | 93 tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
94 tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips2.s | 37 tlt $15,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38 tlt $2,$19,133 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | valid.s | 164 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
165 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | valid.s | 228 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
229 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips32/ |
| H A D | valid.s | 194 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
195 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 231 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
232 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| H A D | valid.s | 231 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
232 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| H A D | valid.s | 232 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
233 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | valid.s | 257 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
258 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 259 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
260 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips64/ |
| H A D | valid.s | 278 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
279 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| H A D | valid.s | 304 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
305 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| H A D | valid.s | 304 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
305 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| H A D | valid.s | 305 tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
306 tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
|