/external/clang/test/CodeGen/ |
H A D | builtins-mips.c | 10 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef 19 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; 27 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; 28 v4i8_b = (v4i8) {2, 4, 6, 8}; 91 v4i8_a = (v4i8) {1, 2, 3, 4}; 124 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; 142 v4i8_a = (v4i8) {1, 2, 3, 4}; 145 v4i8_a = (v4i8) {128, 64, 32, 16}; 168 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; 211 v4i8_b = (v4i8) { [all...] |
H A D | systemz-abi-vector.c | 15 typedef __attribute__((vector_size(4))) char v4i8; typedef 50 v4i8 pass_v4i8(v4i8 arg) { return arg; } 143 struct agg_v4i8 { v4i8 a; }; 166 struct agg_novector1 { v4i8 a; v4i8 b; }; 171 struct agg_novector2 { v4i8 a; float b; }; 176 struct agg_novector3 { v4i8 a; int : 0; }; 181 struct agg_novector4 { v4i8 a __attribute__((aligned (8))); }; 253 v4i8 va_v4i [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 55 v4i8 = 13, // 4 x i8 enumerator in enum:llvm::MVT::SimpleValueType 191 case v4i8 : 226 case v4i8: 258 case v4i8: 340 if (NumElements == 4) return MVT::v4i8;
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 589 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 634 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 652 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 653 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 668 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 676 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 677 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 689 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, [all...] |
H A D | X86ISelLowering.cpp | 794 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom); 800 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom); 835 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); 914 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal); 921 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal); 1068 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal); 1075 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal); 1199 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal); 1208 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal); 1254 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i8, Lega [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineValueType.h | 70 v4i8 = 23, // 4 x i8 234 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || 327 case v4i8: 404 case v4i8: 462 case v4i8: 605 if (NumElements == 4) return MVT::v4i8;
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/external/swiftshader/third_party/LLVM/lib/VMCore/ |
H A D | ValueTypes.cpp | 121 case MVT::v4i8: return "v4i8"; 168 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4);
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/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 155 case MVT::v4i8: return "v4i8"; 233 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, 233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, 275 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
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H A D | AArch64ISelLowering.cpp | 559 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote); 560 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); 2101 case MVT::v4i8: 8619 // %lo = v4i32 sext v4i8 %losrc 8620 // %hi = v4i32 sext v4i8 %hisrc
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/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 140 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 141 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 155 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 156 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
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H A D | ARMISelLowering.cpp | 633 // It is legal to extload from v4i8 to v4i16 or v4i32. 634 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16, 6519 case MVT::v4i8:
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/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 83 case MVT::v4i8: return "MVT::v4i8";
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 70 case MVT::v4i8: return "MVT::v4i8";
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 239 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) { 406 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) { 1221 if (VT.getSimpleVT() == MVT::v4i8) 1741 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); 1922 promoteLdStType(MVT::v4i8, MVT::i32); 1976 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32, 2411 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) && 2544 // We are trying to concat two v2i16 to a single v4i16, or two v4i8 2546 if (ST == MVT::v2i16 || ST == MVT::v4i8)
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 878 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 935 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) 947 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) 974 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 1026 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 130 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); 131 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand); 132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); 186 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
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H A D | R600ISelLowering.cpp | 151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
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H A D | SIISelLowering.cpp | 121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); 2428 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 64 case MVT::v4i8: 1933 case MVT::v4i8: 4011 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) { 4307 case MVT::v4i8:
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