Searched refs:arg (Results 1 - 25 of 218) sorted by relevance

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/hardware/google/av/codec2/include/
H A D_C2MacroUtils.h79 // macros that convert _1, _2, _3, ... to fn(_1, arg), fn(_2, arg), fn(_3, arg), ...
80 #define _C2_MAP_64(fn, arg, head, ...) fn(head, arg), _C2_MAP_63(fn, arg, ##__VA_ARGS__)
81 #define _C2_MAP_63(fn, arg, head, ...) fn(head, arg), _C2_MAP_62(fn, arg, ##__VA_ARGS__)
82 #define _C2_MAP_62(fn, arg, hea
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/hardware/qcom/gps/msm8909w_3100/utils/platform_lib_abstractions/loc_stub/src/
H A Dloc_stub_android_runtime.cpp34 void (*start)(void *), void* arg)
37 pthread_create(&threadId, NULL, (void *(*)(void*))start, arg);
33 createJavaThread(const char* , void (*start)(void *), void* arg) argument
/hardware/intel/img/hwcomposer/merrifield/ips/common/
H A DVsyncControl.cpp50 struct drm_psb_vsync_set_arg arg; local
51 memset(&arg, 0, sizeof(struct drm_psb_vsync_set_arg));
54 arg.vsync.pipe = disp;
57 arg.vsync_operation_mask = VSYNC_ENABLE;
59 arg.vsync_operation_mask = VSYNC_DISABLE;
62 return drm->writeReadIoctl(DRM_PSB_VSYNC_SET, &arg, sizeof(arg));
69 struct drm_psb_vsync_set_arg arg; local
70 memset(&arg, 0, sizeof(struct drm_psb_vsync_set_arg));
72 arg
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H A DWsbmWrapper.c32 struct psb_validate_arg arg; member in struct:PsbWsbmValidateNode
35 static inline uint32_t align_to(uint32_t arg, uint32_t align) argument
37 return ((arg + (align - 1)) & (~(align - 1)));
83 memset(&vNode->arg.d.req, 0, sizeof(vNode->arg.d.req));
109 union drm_psb_extension_arg arg; local
130 strncpy(arg.extension, drmExt, sizeof(drmExt));
132 ret = drmCommandWriteRead(drmFD, 6/*DRM_PSB_EXTENSION*/, &arg, sizeof(arg));
133 if(ret || !arg
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/hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/
H A DVsyncControl.cpp50 struct drm_psb_vsync_set_arg arg; local
51 memset(&arg, 0, sizeof(struct drm_psb_vsync_set_arg));
54 arg.vsync.pipe = disp;
57 arg.vsync_operation_mask = VSYNC_ENABLE;
59 arg.vsync_operation_mask = VSYNC_DISABLE;
62 return drm->writeReadIoctl(DRM_PSB_VSYNC_SET, &arg, sizeof(arg));
69 struct drm_psb_vsync_set_arg arg; local
70 memset(&arg, 0, sizeof(struct drm_psb_vsync_set_arg));
72 arg
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/hardware/qcom/gps/msm8998/utils/platform_lib_abstractions/loc_stub/src/
H A Dloc_stub_android_runtime.cpp34 void (*start)(void *), void* arg)
37 pthread_create(&threadId, NULL, (void *(*)(void*))start, arg);
33 createJavaThread(const char* name, void (*start)(void *), void* arg) argument
/hardware/interfaces/gnss/1.0/default/
H A DThreadCreationWrapper.h33 ThreadFuncArgs(void (*start)(void*), void* arg) : fptr(start), args(arg) {} argument
46 void* threadFunc(void* arg);
50 * holds the pointers to the thread arguments. The arg and start parameters are
55 pthread_t createPthread(const char* name, void (*start)(void*), void* arg,
H A DThreadCreationWrapper.cpp19 void* threadFunc(void* arg) { argument
20 ThreadFuncArgs* threadArgs = reinterpret_cast<ThreadFuncArgs*>(arg);
27 void* arg, std::vector<std::unique_ptr<ThreadFuncArgs>> * listArgs) {
29 auto threadArgs = new ThreadFuncArgs(start, arg);
25 createPthread(const char* name, void (*start)(void*), void* arg, std::vector<std::unique_ptr<ThreadFuncArgs>> * listArgs) argument
/hardware/interfaces/configstore/1.0/vts/functional/
H A DVtsHalConfigstoreV1_0TargetTest.cpp70 [&tmp](OptionalInt64 arg) { tmp = arg.specified; });
74 [&tmp](OptionalInt64 arg) { tmp = arg.specified; });
78 [&tmp](OptionalBool arg) { tmp = arg.specified; });
82 [&tmp](OptionalBool arg) { tmp = arg.specified; });
86 [&tmp](OptionalBool arg) { tmp = arg
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/hardware/qcom/gps/msm8909w_3100/utils/platform_lib_abstractions/loc_stub/include/
H A Dloc_stub_android_runtime.h41 void* arg);
/hardware/qcom/gps/msm8998/utils/platform_lib_abstractions/loc_stub/include/
H A Dloc_stub_android_runtime.h41 void* arg);
/hardware/interfaces/cas/1.0/
H A DICasListener.hal23 * @param arg an integer whose meaning is scheme-specific.
27 onEvent(int32_t event, int32_t arg, vec<uint8_t> data);
/hardware/nxp/secure_element/libese-spi/p73/spm/
H A DphNxpEse_Spm.h56 ESESTATUS phNxpEse_SPM_ConfigPwr(spm_power_t arg);
65 ESESTATUS phNxpEse_SPM_SetState(long arg);
70 ESESTATUS phNxpEse_SPM_SetPwrScheme(long arg);
72 ESESTATUS phNxpEse_SPM_DisablePwrControl(unsigned long arg);
74 ESESTATUS phNxpEse_SPM_SetJcopDwnldState(long arg);
H A DphNxpEse_Spm.cpp94 ESESTATUS phNxpEse_SPM_ConfigPwr(spm_power_t arg) { argument
99 ret = phPalEse_ioctl(phPalEse_e_ChipRst, pEseDeviceHandle, arg);
100 switch (arg) {
251 ESESTATUS phNxpEse_SPM_SetPwrScheme(long arg) { argument
256 __FUNCTION__, arg);
257 ret = phPalEse_ioctl(phPalEse_e_SetPowerScheme, pEseDeviceHandle, arg);
275 ESESTATUS phNxpEse_SPM_DisablePwrControl(unsigned long arg) { argument
280 __FUNCTION__, arg);
281 ret = phPalEse_ioctl(phPalEse_e_DisablePwrCntrl, pEseDeviceHandle, arg);
327 ESESTATUS phNxpEse_SPM_SetJcopDwnldState(long arg) { argument
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/hardware/intel/img/hwcomposer/merrifield/ips/anniedale/
H A DAnnCursorPlane.cpp170 struct drm_psb_register_rw_arg arg; local
171 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
173 arg.plane_enable_mask = 1;
175 arg.plane_disable_mask = 1;
178 arg.plane.type = DC_CURSOR_PLANE;
179 arg.plane.index = mIndex;
180 arg.plane.ctx = 0;
184 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
197 struct drm_psb_register_rw_arg arg; local
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H A DAnnRGBPlane.cpp201 struct drm_psb_register_rw_arg arg; local
202 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
204 arg.plane_enable_mask = 1;
206 arg.plane_disable_mask = 1;
210 arg.plane.type = DC_SPRITE_PLANE;
212 arg.plane.type = DC_PRIMARY_PLANE;
214 arg.plane.index = mIndex;
215 arg.plane.ctx = 0;
219 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
232 struct drm_psb_register_rw_arg arg; local
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/hardware/intel/img/hwcomposer/merrifield/ips/tangier/
H A DTngGrallocBufferMapper.cpp62 struct psb_gtt_mapping_arg arg; local
72 arg.type = PSB_GTT_MAP_TYPE_VIRTUAL;
73 arg.page_align = gttAlign;
74 arg.vaddr = (unsigned long)vaddr;
75 arg.size = size;
78 ret = drm->writeReadIoctl(DRM_PSB_GTT_MAP, &arg, sizeof(arg));
84 VTRACE("offset = %#x", arg.offset_pages);
85 *offset = arg.offset_pages;
91 struct psb_gtt_mapping_arg arg; local
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H A DTngSpritePlane.cpp131 struct drm_psb_register_rw_arg arg; local
132 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
134 arg.plane_enable_mask = 1;
136 arg.plane_disable_mask = 1;
138 arg.plane.type = DC_SPRITE_PLANE;
139 arg.plane.index = mIndex;
140 arg.plane.ctx = 0;
144 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
166 struct drm_psb_register_rw_arg arg; local
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H A DTngCursorPlane.cpp193 struct drm_psb_register_rw_arg arg; local
194 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
196 arg.plane_enable_mask = 1;
198 arg.plane_disable_mask = 1;
201 arg.plane.type = DC_CURSOR_PLANE;
202 arg.plane.index = mIndex;
203 arg.plane.ctx = 0;
207 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
220 struct drm_psb_register_rw_arg arg; local
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H A DTngOverlayPlane.cpp188 struct drm_psb_register_rw_arg arg; local
189 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
192 arg.plane_disable_mask = 1;
194 arg.plane_enable_mask = 1;
196 arg.plane.type = DC_OVERLAY_PLANE;
197 arg.plane.index = mIndex;
198 arg.plane.ctx = (mBackBuffer[mCurrent]->gttOffsetInPage << 12);
200 arg.plane.ctx |= mPipeConfig;
208 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
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H A DTngPrimaryPlane.cpp83 struct drm_psb_register_rw_arg arg; local
84 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
86 arg.plane_enable_mask = 1;
88 arg.plane_disable_mask = 1;
90 arg.plane.type = DC_PRIMARY_PLANE;
91 arg.plane.index = mIndex;
92 arg.plane.ctx = 0;
96 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
/hardware/intel/common/libwsbm/src/
H A Dwsbm_ttmpool.c118 union ttm_pl_create_arg arg; local
134 arg.req.size = size;
135 arg.req.placement = placement;
136 arg.req.page_alignment = alignment / pageSize;
139 arg, ret);
145 dBuf->kBuf.gpuOffset = arg.rep.gpu_offset;
146 dBuf->mapHandle = arg.rep.map_handle;
147 dBuf->realSize = arg.rep.bo_size;
148 dBuf->kBuf.placement = arg.rep.placement;
149 dBuf->kBuf.handle = arg
167 union ttm_pl_reference_arg arg; local
212 struct ttm_pl_reference_req arg; local
252 struct ttm_pl_synccpu_arg arg; local
304 struct ttm_pl_synccpu_arg arg; local
466 union ttm_pl_setstatus_arg arg; local
539 union ttm_pl_create_ub_arg arg; local
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/hardware/intel/img/hwcomposer/moorefield_hdmi/ips/anniedale/
H A DAnnCursorPlane.cpp191 struct drm_psb_register_rw_arg arg; local
192 memset(&arg, 0, sizeof(struct drm_psb_register_rw_arg));
194 arg.plane_enable_mask = 1;
196 arg.plane_disable_mask = 1;
199 arg.plane.type = DC_CURSOR_PLANE;
200 arg.plane.index = mIndex;
201 arg.plane.ctx = 0;
205 bool ret = drm->writeReadIoctl(DRM_PSB_REGISTER_RW, &arg, sizeof(arg));
218 struct drm_psb_register_rw_arg arg; local
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/hardware/broadcom/wlan/bcmdhd/dhdutil/
H A Ddhdu_nl80211.c38 static int dhd_nl_error_handler(struct sockaddr_nl *nla, struct nlmsgerr *err, void *arg) argument
40 int *ret = arg;
45 static int dhd_nl_finish_handler(struct nl_msg *msg, void *arg) argument
47 int *ret = arg;
52 static int dhd_nl_ack_handler(struct nl_msg *msg, void *arg) argument
54 int *ret = arg;
59 static int dhd_nl_valid_handler(struct nl_msg *msg, void *arg) argument
/hardware/intel/img/hwcomposer/moorefield_hdmi/ips/tangier/
H A DTngGrallocBufferMapper.cpp62 struct psb_gtt_mapping_arg arg; local
72 arg.type = PSB_GTT_MAP_TYPE_VIRTUAL;
73 arg.page_align = gttAlign;
74 arg.vaddr = (uint32_t)vaddr;
75 arg.size = size;
78 ret = drm->writeReadIoctl(DRM_PSB_GTT_MAP, &arg, sizeof(arg));
84 VLOGTRACE("offset = %#x", arg.offset_pages);
85 *offset = arg.offset_pages;
91 struct psb_gtt_mapping_arg arg; local
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