| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| H A D | arm64_assembler_test.cpp | 119 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV, enumerator in enum:cond_t
127 "HI", "LS","GE","LT", "GT", "LE", "AL", "NV"
180 {0xA000,INSTR_ADD,AL,AL,0,1,NA,1,MAX_32BIT ,NA,NA,NA,NA,1,0,0,0},
181 {0xA001,INSTR_ADD,AL,AL,0,1,NA,1,MAX_32BIT -1,NA,NA,NA,NA,1,MAX_32BIT,0,0},
182 {0xA002,INSTR_ADD,AL,AL,0,1,NA,0,NA,MAX_32BIT ,NA,NA,NA,1,0,0,0},
183 {0xA003,INSTR_ADD,AL,AL,
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| H A D | load_store.cpp | 37 if (inc) STR(AL, s.reg, addr.reg, immed12_post(4));
38 else STR(AL, s.reg, addr.reg);
43 STRB(AL, s.reg, addr.reg, immed12_pre(0));
44 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
45 STRB(AL, s.reg, addr.reg, immed12_pre(1));
46 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
47 STRB(AL, s.reg, addr.reg, immed12_pre(2));
49 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 16));
52 ADD(AL, 0, addr.reg, addr.reg, imm(3));
55 if (inc) STRH(AL,
[all...] |
| H A D | texturing.cpp | 91 MLA(AL, 0, c, x.reg, dvdx, c);
99 MOV(AL, 0, end, reg_imm(parts.count.reg, LSR, 16));
100 MLA(AL, 1, end, dvdx, end, c);
102 BIC(AL, 0, c, c, reg_imm(c, ASR, 31));
159 AND(AL, 0, parts.iterated.reg,
162 MOV(AL, 0, parts.iterated.reg,
203 ADD(AL, 0, dx, fragment.reg, dx);
220 BIC(AL, 0, fragment.reg, fragment.reg,
348 ADD(AL, 0, Rx, Rx, reg_imm(txPtr.reg, ASR, 16)); // x += (s>>16)
350 ADD(AL,
[all...] |
| H A D | GGLAssembler.cpp | 207 MOV(AL, 0, parts.count.reg,
209 ADD(AL, 0, parts.count.reg, parts.count.reg,
211 MOV(AL, 0, parts.count.reg,
264 AND(AL, 0, parts.dither.reg, parts.count.reg, imm(mask));
265 ADDR_ADD(AL, 0, parts.dither.reg, ctxtReg, parts.dither.reg);
266 LDRB(AL, parts.dither.reg, parts.dither.reg,
323 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16));
338 ADDR_ADD(AL, 0, parts.cbPtr.reg, parts.cbPtr.reg, imm(parts.cbPtr.size>>3));
340 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16));
365 SUB(AL,
[all...] |
| H A D | blending.cpp | 48 LDRB(AL, fogColor.reg, mBuilderContext.Rctx,
56 BIC(AL, 0, factor.reg, factor.reg, reg_imm(factor.reg, ASR, 31));
57 CMP(AL, factor.reg, imm( 0x10000 ));
139 MOV(AL, 0, temp.reg, reg_imm(temp.reg, LSR, temp.l));
149 MOV(AL, 0, fragment.reg, reg_imm(temp.reg, LSR, temp.l));
299 RSB(AL, 0, factor.reg, factor.reg, imm((1<<factor.s)));
332 ADD(AL, 0, factor.reg, fb.reg, reg_imm(fb.reg, LSR, fb.s-1));
337 ADD(AL, 0, factor.reg, fragment.reg,
343 ADD(AL, 0, factor.reg, src_alpha.reg,
350 ADD(AL,
[all...] |
| H A D | Arm64Assembler.cpp | 162 "GE", "LT", "GT", "LE", "AL", "NV"
412 if(cc != AL)
453 if(cc != AL)
465 if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
500 if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
520 if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
528 if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
605 if(cc != AL)
615 if(cc != AL)
622 if(cc != AL)
[all...] |
| H A D | GGLAssembler.h | 35 ADDR_LDR(AL, REG, mBuilderContext.Rctx, immed12_pre(GGL_OFFSETOF(FIELD)))
38 ADDR_STR(AL, REG, mBuilderContext.Rctx, immed12_pre(GGL_OFFSETOF(FIELD)))
41 LDR(AL, REG, mBuilderContext.Rctx, immed12_pre(GGL_OFFSETOF(FIELD)))
44 STR(AL, REG, mBuilderContext.Rctx, immed12_pre(GGL_OFFSETOF(FIELD)))
144 mGen.STR(mGen.AL, reg, mGen.SP, mGen.immed12_pre(-4, 1));
146 mGen.STM(mGen.AL, mGen.DB, mGen.SP, 1, mRegList);
156 mGen.LDR(mGen.AL, reg, mGen.SP, mGen.immed12_post(4));
158 mGen.LDM(mGen.AL, mGen.IA, mGen.SP, 1, mRegList);
|
| H A D | ARMAssembler.cpp | 134 STM(AL, FD, SP, 1, LSAVED);
144 STM(AL, FD, SP, 1, touched | LLR);
147 LDM(AL, FD, SP, 1, touched | LLR);
148 BX(AL, LR);
153 MOV(AL, 0, R0, R0); // NOP
156 BX(AL, LR);
|
| H A D | MIPS64Assembler.cpp | 396 if (cc != AL) {
577 if (cc != AL) {
706 case AL: mMips->B(label); break;
1200 // if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
1208 // if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
| H A D | MIPSAssembler.cpp | 417 if (cc != AL) {
590 if (cc != AL) {
718 case AL: mMips->B(label); break;
|
| H A D | ARMAssemblerInterface.h | 35 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV, enumerator in enum:android::ARMAssemblerInterface::__anon1703
|
| /system/core/libpixelflinger/tests/arch-mips64/assembler/ |
| H A D | mips64_assembler_test.cpp | 120 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV, enumerator in enum:cond_t
128 "HI", "LS","GE","LT", "GT", "LE", "AL", "NV"
188 {0xA000,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT,NA,NA,NA,NA,1,0},
189 {0xA001,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,1,MAX_32BIT-1,NA,NA,NA,NA,1,MAX_64BIT},
190 {0xA002,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT,NA,NA,NA,1,0},
191 {0xA003,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,NA,MAX_32BIT-1,NA,NA,NA,1,MAX_64BIT},
192 {0xA004,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL, 0,NA,1,0},
193 {0xA005,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,MAX_32BIT,SHIFT_LSL,31,NA,1,0xFFFFFFFF80000001},
194 {0xA006,INSTR_ADD,{0,0,0,0,0},AL,0,1,NA,0,0,3,SHIFT_LSR,1,NA,1,2},
195 {0xA007,INSTR_ADD,{0,0,0,0,0},AL,
[all...] |