Searched refs:Rm (Results 1 - 13 of 13) sorted by last modified time

/system/core/libpixelflinger/codeflinger/
H A DARMAssembler.cpp215 int Rd, int Rm, int Rs, int Rn) {
216 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
217 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
219 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
222 int Rd, int Rm, int Rs) {
223 if (Rd == Rm) { int t = Rm; R
214 MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) argument
221 MUL(int cc, int s, int Rd, int Rm, int Rs) argument
227 UMULL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
234 UMUAL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
241 SMULL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
248 SMUAL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
341 SWP(int cc, int Rn, int Rd, int Rm) argument
344 SWPB(int cc, int Rn, int Rd, int Rm) argument
363 CLZ(int cc, int Rd, int Rm) argument
368 QADD(int cc, int Rd, int Rm, int Rn) argument
373 QDADD(int cc, int Rd, int Rm, int Rn) argument
378 QSUB(int cc, int Rd, int Rm, int Rn) argument
383 QDSUB(int cc, int Rd, int Rm, int Rn) argument
388 SMUL(int cc, int xy, int Rd, int Rm, int Rs) argument
394 SMULW(int cc, int y, int Rd, int Rm, int Rs) argument
400 SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn) argument
406 SMLAL(int cc, int xy, int RdHi, int RdLo, int Rs, int Rm) argument
412 SMLAW(int cc, int y, int Rd, int Rm, int Rs, int Rn) argument
423 UXTB16(int cc, int Rd, int Rm, int rotate) argument
496 reg_imm(int Rm, int type, uint32_t shift) argument
501 reg_rrx(int Rm) argument
506 reg_reg(int Rm, int type, int Rs) argument
531 reg_scale_pre(int Rm, int type, uint32_t shift, int W) argument
539 reg_scale_post(int Rm, int type, uint32_t shift) argument
569 reg_pre(int Rm, int W) argument
574 reg_post(int Rm) argument
[all...]
H A DARMAssembler.h70 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
71 virtual uint32_t reg_rrx(int Rm);
72 virtual uint32_t reg_reg(int Rm, int type, int Rs);
76 // (immediate and Rm can be negative, which indicates U=0)
79 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
80 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
83 // (immediate and Rm can be negative, which indicates U=0)
86 virtual uint32_t reg_pre(int Rm, int W=0);
87 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, in
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H A DARMAssemblerInterface.h81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
82 virtual uint32_t reg_rrx(int Rm) = 0;
83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
87 // (immediate and Rm can be negative, which indicates U=0)
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0;
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0;
94 // (immediate and Rm can be negative, which indicates U=0)
97 virtual uint32_t reg_pre(int Rm, int W=0) = 0;
98 virtual uint32_t reg_post(int Rm) = 0;
129 int Rd, int Rm, in
289 SMULBB(int cc, int Rd, int Rm, int Rs) argument
291 SMULTB(int cc, int Rd, int Rm, int Rs) argument
293 SMULBT(int cc, int Rd, int Rm, int Rs) argument
295 SMULTT(int cc, int Rd, int Rm, int Rs) argument
298 SMULWB(int cc, int Rd, int Rm, int Rs) argument
300 SMULWT(int cc, int Rd, int Rm, int Rs) argument
304 SMLABB(int cc, int Rd, int Rm, int Rs, int Rn) argument
307 SMLATB(int cc, int Rd, int Rm, int Rs, int Rn) argument
310 SMLABT(int cc, int Rd, int Rm, int Rs, int Rn) argument
313 SMLATT(int cc, int Rd, int Rm, int Rs, int Rn) argument
317 SMLALBB(int cc, int RdHi, int RdLo, int Rs, int Rm) argument
320 SMLALTB(int cc, int RdHi, int RdLo, int Rs, int Rm) argument
323 SMLALBT(int cc, int RdHi, int RdLo, int Rs, int Rm) argument
326 SMLALTT(int cc, int RdHi, int RdLo, int Rs, int Rm) argument
330 SMLAWB(int cc, int Rd, int Rm, int Rs, int Rn) argument
333 SMLAWT(int cc, int Rd, int Rm, int Rs, int Rn) argument
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H A DARMAssemblerProxy.cpp93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift) argument
95 return mTarget->reg_imm(Rm, type, shift);
98 uint32_t ARMAssemblerProxy::reg_rrx(int Rm) argument
100 return mTarget->reg_rrx(Rm);
103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs) argument
105 return mTarget->reg_reg(Rm, type, Rs);
111 // (immediate and Rm can be negative, which indicates U=0)
122 uint32_t ARMAssemblerProxy::reg_scale_pre(int Rm, int type, uint32_t shift, int W) argument
124 return mTarget->reg_scale_pre(Rm, type, shift, W);
127 uint32_t ARMAssemblerProxy::reg_scale_post(int Rm, in argument
145 reg_pre(int Rm, int W) argument
150 reg_post(int Rm) argument
166 MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) argument
169 MUL(int cc, int s, int Rd, int Rm, int Rs) argument
172 UMULL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
176 UMUAL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
180 SMULL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
184 SMUAL(int cc, int s, int RdLo, int RdHi, int Rm, int Rs) argument
243 SWP(int cc, int Rn, int Rd, int Rm) argument
246 SWPB(int cc, int Rn, int Rd, int Rm) argument
257 CLZ(int cc, int Rd, int Rm) argument
260 QADD(int cc, int Rd, int Rm, int Rn) argument
263 QDADD(int cc, int Rd, int Rm, int Rn) argument
266 QSUB(int cc, int Rd, int Rm, int Rn) argument
269 QDSUB(int cc, int Rd, int Rm, int Rn) argument
272 SMUL(int cc, int xy, int Rd, int Rm, int Rs) argument
275 SMULW(int cc, int y, int Rd, int Rm, int Rs) argument
278 SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn) argument
281 SMLAL( int cc, int xy, int RdHi, int RdLo, int Rs, int Rm) argument
285 SMLAW(int cc, int y, int Rd, int Rm, int Rs, int Rn) argument
289 UXTB16(int cc, int Rd, int Rm, int rotate) argument
[all...]
H A DARMAssemblerProxy.h59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
60 virtual uint32_t reg_rrx(int Rm);
61 virtual uint32_t reg_reg(int Rm, int type, int Rs);
65 // (immediate and Rm can be negative, which indicates U=0)
68 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
69 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
72 // (immediate and Rm can be negative, which indicates U=0)
75 virtual uint32_t reg_pre(int Rm, int W=0);
76 virtual uint32_t reg_post(int Rm);
83 int Rd, int Rm, in
[all...]
H A DArm64Assembler.cpp375 uint32_t Rm; local
381 Rm = mAddrMode.reg_imm_Rm;
387 Rm = Op2;
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
471 int Rm = mAddrMode.reg_imm_Rm; local
473 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amoun
477 int Rm = Op2; local
487 int Rm = mTmpReg1; local
518 MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn) argument
526 MUL(int cc, int s, int Rd, int Rm, int Rs) argument
773 SMUL(int cc, int xy, int Rd, int Rm, int Rs) argument
793 SMULW(int cc, int y, int Rd, int Rm, int Rs) argument
809 SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn) argument
836 UXTB16(int cc, int Rd, int Rm, int rotate) argument
884 reg_imm(int Rm, int type, uint32_t shift) argument
924 reg_scale_pre(int Rm, int type, uint32_t shift, int W) argument
963 reg_pre(int Rm, int W) argument
1001 A64_LDRSTR_Wm_SXTW_0(uint32_t op, uint32_t size, uint32_t Rt, uint32_t Rn, uint32_t Rm) argument
1044 A64_ADD_X_Wm_SXTW(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t amount) argument
1055 A64_SUB_X_Wm_SXTW(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t amount) argument
1072 A64_ADD_X(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t shift, uint32_t amount) argument
1095 A64_ADD_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t shift, uint32_t amount) argument
1105 A64_SUB_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t shift, uint32_t amount, uint32_t setflag) argument
1126 A64_AND_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t shift, uint32_t amount) argument
1136 A64_ORR_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t shift, uint32_t amount) argument
1146 A64_ORN_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t shift, uint32_t amount) argument
1156 A64_CSEL_X(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t cond) argument
1163 A64_CSEL_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t cond) argument
1197 A64_SMADDL(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t Ra) argument
1204 A64_MADD_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t Ra) argument
1233 A64_EXTR_W(uint32_t Rd, uint32_t Rn, uint32_t Rm, uint32_t lsb) argument
[all...]
H A DArm64Assembler.h83 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
84 virtual uint32_t reg_rrx(int Rm);
85 virtual uint32_t reg_reg(int Rm, int type, int Rs);
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
94 virtual uint32_t reg_pre(int Rm, int W=0);
95 virtual uint32_t reg_post(int Rm);
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
106 int RdLo, int RdHi, int Rm, in
[all...]
H A DMIPS64Assembler.cpp221 uint32_t ArmToMips64Assembler::reg_imm(int Rm, int type, uint32_t shift) argument
223 amode.reg = Rm;
229 uint32_t ArmToMips64Assembler::reg_rrx(int Rm __unused)
235 uint32_t ArmToMips64Assembler::reg_reg(int Rm __unused, int type __unused,
244 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
265 uint32_t ArmToMips64Assembler::reg_scale_pre(int Rm, int type, argument
270 amode.reg = Rm;
277 uint32_t ArmToMips64Assembler::reg_scale_post(int Rm __unused, int type __unused,
284 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
304 uint32_t ArmToMips64Assembler::reg_pre(int Rm, in argument
594 MLA(int cc __unused, int s, int Rd, int Rm, int Rs, int Rn) argument
608 MUL(int cc __unused, int s, int Rd, int Rm, int Rs) argument
618 UMULL(int cc __unused, int s, int RdLo, int RdHi, int Rm, int Rs) argument
1028 CLZ(int cc __unused, int Rd, int Rm) argument
1071 SMUL(int cc __unused, int xy, int Rd, int Rm, int Rs) argument
1100 SMULW(int cc __unused, int y, int Rd, int Rm, int Rs) argument
1119 SMLA(int cc __unused, int xy, int Rd, int Rm, int Rs, int Rn) argument
1170 UXTB16(int cc __unused, int Rd, int Rm, int rotate) argument
[all...]
H A DMIPS64Assembler.h73 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
74 virtual uint32_t reg_rrx(int Rm);
75 virtual uint32_t reg_reg(int Rm, int type, int Rs);
79 // (immediate and Rm can be negative, which indicates U=0)
82 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
83 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
86 // (immediate and Rm can be negative, which indicates U=0)
89 virtual uint32_t reg_pre(int Rm, int W=0);
90 virtual uint32_t reg_post(int Rm);
99 int Rd, int Rm, in
[all...]
H A DMIPSAssembler.cpp232 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift) argument
234 amode.reg = Rm;
240 uint32_t ArmToMipsAssembler::reg_rrx(int Rm __unused)
246 uint32_t ArmToMipsAssembler::reg_reg(int Rm __unused, int type __unused,
255 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
276 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type, argument
281 amode.reg = Rm;
288 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm __unused, int type __unused,
295 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
319 uint32_t ArmToMipsAssembler::reg_pre(int Rm, in argument
607 MLA(int cc __unused, int s, int Rd, int Rm, int Rs, int Rn) argument
620 MUL(int cc __unused, int s, int Rd, int Rm, int Rs) argument
630 UMULL(int cc __unused, int s, int RdLo, int RdHi, int Rm, int Rs) argument
1040 CLZ(int cc __unused, int Rd, int Rm) argument
1083 SMUL(int cc __unused, int xy, int Rd, int Rm, int Rs) argument
1122 SMULW(int cc __unused, int y, int Rd, int Rm, int Rs) argument
1142 SMLA(int cc __unused, int xy, int Rd, int Rm, int Rs, int Rn) argument
1203 UXTB16(int cc __unused, int Rd, int Rm, int rotate) argument
[all...]
H A DMIPSAssembler.h68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
69 virtual uint32_t reg_rrx(int Rm);
70 virtual uint32_t reg_reg(int Rm, int type, int Rs);
74 // (immediate and Rm can be negative, which indicates U=0)
77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
81 // (immediate and Rm can be negative, which indicates U=0)
84 virtual uint32_t reg_pre(int Rm, int W=0);
85 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, in
[all...]
/system/core/libpixelflinger/tests/arch-arm64/assembler/
H A Darm64_assembler_test.cpp414 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
439 op2 = Rm;
440 regs[Rm] = test.RmValue;
444 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
445 regs[Rm] = test.RmValue;
455 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
460 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
461 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,R
752 uint32_t Rd, Rm, Rs, Rn; local
[all...]
/system/core/libpixelflinger/tests/arch-mips64/assembler/
H A Dmips64_assembler_test.cpp372 uint32_t Rn = R_t0, uint32_t Rm = R_t1, uint32_t Rs = R_t2)
401 op2 = Rm;
402 regs[Rm] = (int64_t)((int32_t)(test.RmValue));
406 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
407 regs[Rm] = (int64_t)((int32_t)(test.RmValue));
417 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
418 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
422 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
423 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
424 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,R
[all...]

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