Searched refs:imm (Results 1 - 20 of 20) sorted by path

/system/core/libpixelflinger/codeflinger/
H A DARMAssembler.cpp444 uint32_t immediate, uint32_t& rot, uint32_t& imm)
447 imm = immediate;
448 if (imm > 0x7F) { // skip the easy cases
449 while (!(imm&3) || (imm&0xFC000000)) {
451 newval = imm >> 2;
452 newval |= (imm&3) << 30;
453 imm = newval;
463 if (imm>=0x100)
466 if (((imm>>(ro
443 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
476 uint32_t rot, imm; local
480 uint32_t ARMAssembler::imm(uint32_t immediate) function in class:android::ARMAssembler
482 uint32_t rot, imm; local
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H A DARMAssembler.h67 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
69 virtual uint32_t imm(uint32_t immediate);
H A DARMAssemblerInterface.h78 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) = 0;
80 virtual uint32_t imm(uint32_t immediate) = 0;
H A DARMAssemblerProxy.cpp81 int ARMAssemblerProxy::buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm) argument
83 return mTarget->buildImmediate(i, rot, imm);
88 uint32_t ARMAssemblerProxy::imm(uint32_t immediate) function in class:android::ARMAssemblerProxy
90 return mTarget->imm(immediate);
H A DARMAssemblerProxy.h56 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
58 virtual uint32_t imm(uint32_t immediate);
H A DArm64Assembler.cpp365 int imm = mAddrMode.immediate; local
366 *mPC++ = A64_MOVZ_W(mTmpReg2, imm & 0x0000FFFF, 0);
367 *mPC++ = A64_MOVK_W(mTmpReg2, (imm >> 16) & 0x0000FFFF, 16);
483 int imm = mAddrMode.immediate; local
484 *mPC++ = A64_MOVZ_W(mTmpReg1, imm & 0x0000FFFF, 0);
485 *mPC++ = A64_MOVK_W(mTmpReg1, (imm >> 16) & 0x0000FFFF, 16);
586 int imm = mAddrMode.immediate; local
587 if(imm >= 0 && imm < (1<<12))
588 *mPC++ = A64_ADD_IMM_X(mTmpReg1, mZeroReg, imm,
842 uint32_t imm = 0x00FF00FF; local
859 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
870 uint32_t rot, imm; local
874 uint32_t ArmToArm64Assembler::imm(uint32_t immediate) function in class:android::ArmToArm64Assembler
1081 A64_ADD_IMM_X(uint32_t Rd, uint32_t Rn, uint32_t imm, uint32_t shift) argument
1088 A64_SUB_IMM_X(uint32_t Rd, uint32_t Rn, uint32_t imm, uint32_t shift) argument
1176 A64_MOVZ_X(uint32_t Rd, uint32_t imm, uint32_t shift) argument
1183 A64_MOVK_W(uint32_t Rd, uint32_t imm, uint32_t shift) argument
1190 A64_MOVZ_W(uint32_t Rd, uint32_t imm, uint32_t shift) argument
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H A DArm64Assembler.h80 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
82 virtual uint32_t imm(uint32_t immediate);
210 uint32_t imm, uint32_t shift = 0);
212 uint32_t imm, uint32_t shift = 0);
228 uint32_t A64_MOVZ_W(uint32_t Rd, uint32_t imm, uint32_t shift);
229 uint32_t A64_MOVZ_X(uint32_t Rd, uint32_t imm, uint32_t shift);
230 uint32_t A64_MOVK_W(uint32_t Rd, uint32_t imm, uint32_t shift);
H A DGGLAssembler.cpp210 imm( 1 << (32 - GGL_DITHER_ORDER_SHIFT)));
264 AND(AL, 0, parts.dither.reg, parts.count.reg, imm(mask));
323 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16));
338 ADDR_ADD(AL, 0, parts.cbPtr.reg, parts.cbPtr.reg, imm(parts.cbPtr.size>>3));
340 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16));
366 SUB(AL, 0, parts.count.reg, parts.count.reg, imm(1));
376 AND(AL, 0, tx, Rx, imm(GGL_DITHER_MASK));
377 AND(AL, 0, ty, Ry, imm(GGL_DITHER_MASK));
830 case GGL_CLEAR: MOV(AL, 0, pixel.reg, imm(0)); break;
852 case GGL_SET: MVN(AL, 0, pixel.reg, imm(
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H A DMIPS64Assembler.cpp199 uint32_t immediate, uint32_t& rot, uint32_t& imm)
203 imm = immediate;
215 uint32_t ArmToMips64Assembler::imm(uint32_t immediate) function in class:android::ArmToMips64Assembler
352 // this works with the imm(), reg_imm() methods above, which are directly
1385 void MIPS64Assembler::DADDIU(int Rt, int Rs, int16_t imm) argument
1387 *mPC++ = (daddiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1396 void MIPS64Assembler::DSUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) argument
1398 *mPC++ = (daddiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) & MSK_16);
198 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
H A DMIPS64Assembler.h70 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
72 virtual uint32_t imm(uint32_t immediate);
274 void DADDIU(int Rt, int Rs, int16_t imm);
276 void DSUBIU(int Rt, int Rs, int16_t imm);
H A DMIPSAssembler.cpp43 ** Refactored ARM address-mode static functions (imm(), reg_imm(), imm12_pre(), etc.)
209 uint32_t immediate, uint32_t& rot, uint32_t& imm)
213 imm = immediate;
225 uint32_t ArmToMipsAssembler::imm(uint32_t immediate) function in class:android::ArmToMipsAssembler
367 // this works with the imm(), reg_imm() methods above, which are directly
1445 // MD00086 pdf says this is: ADDIU rt, rs, imm -- they do not use Rd
1446 void MIPSAssembler::ADDIU(int Rt, int Rs, int16_t imm) argument
1448 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1459 void MIPSAssembler::SUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j) argument
1461 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm)
208 buildImmediate( uint32_t immediate, uint32_t& rot, uint32_t& imm) argument
1533 SLTI(int Rt, int Rs, int16_t imm) argument
1545 SLTIU(int Rt, int Rs, int16_t imm) argument
1563 ANDI(int Rt, int Rs, uint16_t imm) argument
1575 ORI(int Rt, int Rs, uint16_t imm) argument
1597 XORI(int Rt, int Rs, uint16_t imm) argument
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H A DMIPSAssembler.h65 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
67 virtual uint32_t imm(uint32_t immediate);
274 void ADDIU(int Rt, int Rs, int16_t imm);
276 void SUBIU(int Rt, int Rs, int16_t imm);
295 void SLTI(int Rt, int Rs, int16_t imm);
297 void SLTIU(int Rt, int Rs, int16_t imm);
306 void ANDI(int Rd, int Rs, uint16_t imm);
308 void ORI(int Rt, int Rs, uint16_t imm);
312 void XORI(int Rt, int Rs, uint16_t imm);
H A Dblending.cpp57 CMP(AL, factor.reg, imm( 0x10000 ));
58 MOV(HS, 0, factor.reg, imm( 0x10000 ));
299 RSB(AL, 0, factor.reg, factor.reg, imm((1<<factor.s)));
366 RSB(AL, 0, factor.reg, factor.reg, imm((1<<factor.s)));
659 CMP(AL, v.reg, imm( 1<<v.h ));
661 MOV(HS, 0, v.reg, imm( one ));
663 MVN(HS, 0, v.reg, imm( ~one ));
665 MOV(HS, 0, v.reg, imm( 1<<v.h ));
666 SUB(HS, 0, v.reg, v.reg, imm( 1<<v.l ));
H A Dload_store.cpp52 ADD(AL, 0, addr.reg, addr.reg, imm(3));
96 ADD(AL, 0, addr.reg, addr.reg, imm(3));
123 AND(AL, 0, d.reg, s, imm(mask)); // component = packed & mask;
125 BIC(AL, 0, d.reg, s, imm(~mask)); // component = packed & mask;
H A Dmips64_disassem.c378 print_addr(loc + 4 + ((short)i.IType.imm << 2));
487 db_printf("%d(%s)", (short)i.IType.imm,
496 i.IType.imm);
504 i.IType.imm);
510 i.IType.imm);
514 (short)i.IType.imm);
523 (short)i.IType.imm);
531 (short)i.IType.imm);
H A Dmips_disassem.c377 print_addr(loc + 4 + ((short)i.IType.imm << 2));
486 db_printf("%d(%s)", (short)i.IType.imm,
495 i.IType.imm);
503 i.IType.imm);
509 i.IType.imm);
516 i.IType.imm,
527 (short)i.IType.imm);
535 (short)i.IType.imm);
H A Dmips_opcode.h52 unsigned imm: 16; member in struct:__anon1721::__anon1722
87 unsigned imm: 16; member in struct:__anon1721::__anon1726
H A Dtexturing.cpp160 parts.iterated.reg, imm(0xFF));
513 SUB(AL, 0, u, u, imm(1<<(FRAC_BITS-1)));
514 SUB(AL, 0, v, v, imm(1<<(FRAC_BITS-1)));
517 AND(AL, 0, U, u, imm((1<<FRAC_BITS)-1));
518 AND(AL, 0, V, v, imm((1<<FRAC_BITS)-1));
521 SUB(AL, 0, width, width, imm(1));
522 SUB(AL, 0, height, height, imm(1));
531 MOV(LT, 0, width, imm(1 << shift));
534 RSB(GE, 0, width, width, imm(0));
551 MOV(LE, 0, width, imm(
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/system/core/libpixelflinger/tests/arch-arm64/assembler/
H A Darm64_assembler_test.cpp435 op2 = a64asm->imm(test.immValue);
683 uint32_t op2 = a64asm->imm(0x31);
/system/core/libpixelflinger/tests/arch-mips64/assembler/
H A Dmips64_assembler_test.cpp397 op2 = a64asm->imm(test.immValue);

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