/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 113 // P0 = cmp.eq(Rs,#u2) 125 // Rd = Rs 166 // Rd=Rs ; jump #r9:2 207 MCOperand Rs, Rt; local 229 Rs = L.getOperand(1); 235 CompoundInsn->addOperand(Rs); 242 Rs = L.getOperand(1); 248 CompoundInsn->addOperand(Rs); 255 Rs = L.getOperand(1); 261 CompoundInsn->addOperand(Rs); [all...] |
/external/mesa3d/src/mesa/swrast/ |
H A D | s_blend.c | 480 const GLfloat Rs = rgba[i][RCOMP]; local 554 sR = Rs; 559 sR = 1.0F - Rs; 632 dR = Rs; 637 dR = 1.0F - Rs; 740 r = Rs * sR + Rd * dR; 746 r = Rs * sR - Rd * dR; 752 r = Rd * dR - Rs * sR; 758 r = MIN2( Rd, Rs ); 763 r = MAX2( Rd, Rs ); [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 365 MCOperand &Rs = Inst.getOperand(1); local 366 assert (Rs.isReg() && "Expected register and none was found"); 367 unsigned Reg = RI->getEncodingValue(Rs.getReg()); 372 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); 435 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd 498 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
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H A D | HexagonBitSimplify.cpp | 67 RegisterSet &insert(const RegisterSet &Rs) { argument 68 return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); 70 RegisterSet &remove(const RegisterSet &Rs) { argument 71 return static_cast<RegisterSet&>(BitVector::reset(Rs)); 94 bool includes(const RegisterSet &Rs) const { 96 return !Rs.BitVector::test(*this); 98 bool intersects(const RegisterSet &Rs) const { 99 return BitVector::anyCommon(Rs); 1674 BitTracker::RegisterRef &Rs, BitTracker::RegisterRef &Rt); 1780 // set the inputs Rs an [all...] |
H A D | HexagonGenInsert.cpp | 109 RegisterSet &insert(const RegisterSet &Rs) { argument 110 return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); 112 RegisterSet &remove(const RegisterSet &Rs) { argument 113 return static_cast<RegisterSet&>(BitVector::reset(Rs)); 136 bool includes(const RegisterSet &Rs) const { 138 return !Rs.BitVector::test(*this); 140 bool intersects(const RegisterSet &Rs) const { 141 return BitVector::anyCommon(Rs); 1195 void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, 1232 void IFOrdering::stats(const RegisterSet &Rs, unsigne [all...] |
H A D | HexagonSplitDouble.cpp | 81 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs); 122 const USet &Rs = I.second; local 123 if (Rs.find(Reg) != Rs.end()) 431 USet &Rs) { 514 Rs.insert(DP.begin(), End); 515 Rs.insert(CmpR1); 516 Rs.insert(CmpR2); 520 dump_partition(dbgs(), Rs, *TRI); 537 USet Rs; local 430 collectIndRegsForLoop(const MachineLoop *L, USet &Rs) argument [all...] |
H A D | RDFGraph.cpp | 1333 const auto &Rs = RefM[DBA.Id]; local 1334 Refs.insert(Rs.begin(), Rs.end());
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H A D | HexagonFrameLowering.cpp | 115 // Rd = ALLOCA Rs, A 118 // Rs - minimum size (the actual allocated can be larger to accommodate 2187 // Rd = alloca Rs, #A 2189 // If Rs and Rd are different registers, use this sequence: 2190 // Rd = sub(r29, Rs) 2191 // r29 = sub(r29, Rs) 2196 // Rd = sub(r29, Rs) 2203 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local 2205 // Rd = sub(r29, Rs) 2208 .addReg(Rs); [all...] |
H A D | HexagonInstrInfo.cpp | 1240 unsigned Rs = Op2.getReg(); local 1246 if (Rd != Rs) 1249 .addReg(Rs, K2); 3329 // P0 = cmp.eq(Rs,#u2) 3340 // Rd = Rs 3378 // Rd=Rs ; jump #r9:2 3647 // Rd = memw(Rs+#u4:2) 3648 // Rd = memub(Rs+#u4:0) 3660 // Rd = memw(Rs+#u4:2) 3668 // Rd = memub(Rs [all...] |
/external/capstone/arch/Mips/ |
H A D | MipsDisassembler.c | 536 uint32_t Rs = fieldFromInstruction(insn, 21, 5); local 541 if (Rs >= Rt) { 544 } else if (Rs != 0 && Rs < Rt) { 551 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); 572 uint32_t Rs = fieldFromInstruction(insn, 21, 5); local 577 if (Rs >= Rt) { 580 } else if (Rs != 0 && Rs < Rt) { 587 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); 609 uint32_t Rs = fieldFromInstruction(insn, 21, 5); local 651 uint32_t Rs = fieldFromInstruction(insn, 21, 5); local 689 uint32_t Rs = fieldFromInstruction(insn, 21, 5); local 735 uint32_t Rs = fieldFromInstruction(insn, 21, 5); local [all...] |
/external/capstone/arch/AArch64/ |
H A D | AArch64Disassembler.c | 1196 unsigned Rs = fieldFromInstruction(insn, 16, 5); local 1208 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1226 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1236 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1245 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
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/external/eigen/Eigen/src/UmfPackSupport/ |
H A D | UmfPackSupport.h | 109 int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) 111 return umfpack_di_get_numeric(Lp,Lj,Lx,Up,Ui,Ux,P,Q,Dx,do_recip,Rs,Numeric); 115 int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) 121 Dx?&dx0_real:0,0,do_recip,Rs,Numeric); 108 umfpack_get_numeric(int Lp[], int Lj[], double Lx[], int Up[], int Ui[], double Ux[], int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) argument 114 umfpack_get_numeric(int Lp[], int Lj[], std::complex<double> Lx[], int Up[], int Ui[], std::complex<double> Ux[], int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) argument
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/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1087 unsigned Rs = fieldFromInstruction(insn, 16, 5); local 1099 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1123 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1135 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1144 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 1317 // shifted. The second is Rs, the amount to shift by, and the third specifies 1323 // {11-8} = Rs 1336 unsigned Rs = MO1.getReg(); local 1337 if (Rs) { 1354 // Encode the shift operation Rs. 1355 // Encode Rs bit[11:8]. 1357 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
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/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 602 InsnType Rs = fieldFromInstruction(insn, 21, 5); local 607 if (Rs >= Rt) { 610 } else if (Rs != 0 && Rs < Rt) { 618 Rs))); 632 InsnType Rs = fieldFromInstruction(insn, 16, 5); local 635 if (Rs >= Rt) { 640 Rs))); 641 } else if (Rs != 0 && Rs < R 672 InsnType Rs = fieldFromInstruction(insn, 21, 5); local 702 InsnType Rs = fieldFromInstruction(insn, 16, 5); local 743 InsnType Rs = fieldFromInstruction(insn, 21, 5); local 788 InsnType Rs = fieldFromInstruction(insn, 21, 5); local 830 InsnType Rs = fieldFromInstruction(insn, 21, 5); local 879 InsnType Rs = fieldFromInstruction(insn, 21, 5); local 2287 InsnType Rs = fieldFromInstruction(insn, 16, 5); local 2333 InsnType Rs = fieldFromInstruction(insn, 16, 5); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 931 unsigned Rs = MO1.getReg(); local 932 if (Rs) { 965 // Encode the shift operation Rs or shift_imm (except rrx). 966 if (Rs) { 967 // Encode Rs bit[11:8]. 969 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1326 // Encode Rs
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 1089 // shifted. The second is Rs, the amount to shift by, and the third specifies 1095 // {11-8} = Rs 1108 unsigned Rs = MO1.getReg(); local 1109 if (Rs) { 1126 // Encode the shift operation Rs. 1127 // Encode Rs bit[11:8]. 1129 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
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/external/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 802 SmallVector<const SCEV *, 2> Qs, Rs; local 814 Rs.push_back(R); 819 Remainder = Rs[0]; 824 Remainder = SE.getAddExpr(Rs);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1062 unsigned Rs = fieldFromInstruction32(Val, 8, 4); local 1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
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/external/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); local 212 Opcode |= Rs << 21; 222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); local 224 Opcode |= Rs << 21; 237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); local 248 Opcode |= Rs << 21; 259 const IValueT Rs local 285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); local 528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); local 656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); local 820 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); local 837 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); local 872 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); local 910 IValueT Rs = encodeGPRegister(OpRs, "Rs", "mthi"); local 917 IValueT Rs = encodeGPRegister(OpRs, "Rs", "mtlo"); local 1151 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "teq"); local 1226 IValueT Rs = encodeGPRegister(OpRs, "Rs", "branch"); local [all...] |
/external/vixl/src/aarch64/ |
H A D | assembler-aarch64.h | 2620 static Instr Rs(CPURegister rs) { function in class:vixl::aarch64::Assembler
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/external/capstone/arch/ARM/ |
H A D | ARMDisassembler.c | 1206 unsigned Rs = fieldFromInstruction_4(Val, 8, 4); local 1211 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
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/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1179 unsigned Rs = fieldFromInstruction(Val, 8, 4); local 1184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
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/external/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1598 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" 1844 MCOperand &Rs = Inst.getOperand(2); local 1852 TmpInst.addOperand(Rs); 1863 MCOperand &Rs = Inst.getOperand(2); local 1871 TmpInst.addOperand(Rs); 1882 MCOperand &Rs = Inst.getOperand(2); local 1890 TmpInst.addOperand(Rs); 1904 MCOperand &Rs = Inst.getOperand(1); local 1927 TmpInst.addOperand(Rs); 1940 if (Value == 0) { // convert to $Rd = $Rs 1943 MCOperand &Rs = Inst.getOperand(1); local 1953 MCOperand &Rs = Inst.getOperand(1); local 1995 MCOperand &Rs = Inst.getOperand(1); local 2014 MCOperand &Rs = Inst.getOperand(1); local 2151 MCOperand &Rs = Inst.getOperand(1); local [all...] |