Searched refs:Opc (Results 1 - 25 of 289) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp43 unsigned Opc = MI.getOpcode(); local
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
65 unsigned Opc = MI.getOpcode(); local
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc
83 unsigned Opc = 0, ZeroReg = 0; local
190 unsigned Opc = 0; local
258 unsigned Opc = 0; local
334 unsigned Opc; local
454 unsigned Opc = ABI.GetPtrAdduOp(); local
537 compareOpndSize(unsigned Opc, const MachineFunction &MF) const argument
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H A DMips16InstrInfo.cpp63 unsigned Opc = 0; local
67 Opc = Mips::MoveR3216;
70 Opc = Mips::Move32R16;
73 Opc = Mips::Mfhi16, SrcReg = 0;
77 Opc = Mips::Mflo16, SrcReg = 0;
80 assert(Opc && "Cannot copy registers");
82 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
100 unsigned Opc = 0; local
102 Opc = Mips::SwRxSpImmX16;
103 assert(Opc
118 unsigned Opc = 0; local
203 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; local
233 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? local
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H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
21 Inst(unsigned Opc, unsigned ImmOpnd);
H A DMipsSEInstrInfo.h66 unsigned getOppositeBranchOpc(unsigned Opc) const override;
80 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
86 std::pair<bool, bool> compareOpndSize(unsigned Opc,
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsInstrInfo.cpp51 unsigned Opc = MI->getOpcode(); local
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc
76 unsigned Opc = MI->getOpcode(); local
106 unsigned Opc = 0, ZeroReg = 0; local
172 unsigned Opc = 0; local
198 unsigned Opc = 0; local
228 GetAnalyzableBrOpc(unsigned Opc) argument
239 GetOppositeBranchOpc(unsigned Opc) argument
260 AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, MachineBasicBlock *&BB, SmallVectorImpl<MachineOperand>& Cond) argument
359 unsigned Opc = Cond[0].getImm(); local
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H A DMipsAsmPrinter.cpp47 static bool isUnalignedLoadStore(unsigned Opc) { argument
48 return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
49 Opc == Mips::USW || Opc == Mips::USH ||
50 Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
51 Opc
64 unsigned Opc = MI->getOpcode(); local
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/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h103 // Return the non-pre/post incrementing version of 'Opc'. Return 0
105 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
420 bool isUncondBranchOpcode(int Opc) { argument
421 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
425 bool isCondBranchOpcode(int Opc) { argument
426 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
430 isJumpTableBranchOpcode(int Opc) argument
436 isIndirectBranchOpcode(int Opc) argument
440 isPopOpcode(int Opc) argument
446 isPushOpcode(int Opc) argument
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H A DARMInstrInfo.h31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp622 unsigned Opc; local
626 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
629 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
632 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
635 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
638 ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0),
645 unsigned Opc; local
649 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
653 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
657 Opc
2751 unsigned Opc = 0; local
3137 unsigned Opc = 0; local
3661 unsigned Opc = 0; local
5038 unsigned Opc; local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMInstrInfo.h31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
33 unsigned getUnindexedOpcode(unsigned Opc) const;
H A DARMBaseInstrInfo.h38 // Return the non-pre/post incrementing version of 'Opc'. Return 0
40 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
315 bool isUncondBranchOpcode(int Opc) { argument
316 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
320 bool isCondBranchOpcode(int Opc) { argument
321 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
325 isJumpTableBranchOpcode(int Opc) argument
331 isIndirectBranchOpcode(int Opc) argument
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H A DARMInstrInfo.cpp30 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
31 switch (Opc) {
H A DARMISelDAGToDAG.cpp115 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
118 SDValue &Offset, SDValue &Opc);
120 SDValue &Opc) {
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
125 SDValue &Opc) {
126 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
130 SDValue &Opc) {
131 SelectAddrMode2Worker(N, Base, Offset, Opc);
132 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
138 SDValue &Offset, SDValue &Opc);
119 SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
124 SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
129 SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
307 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
390 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument
413 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument
491 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
589 SelectAddrMode2Worker(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
724 SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
760 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
780 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
805 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
853 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
1154 SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, SDValue &Opc) argument
1609 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
1751 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
1911 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
1975 unsigned Opc = Opcodes[OpcodeIndex]; local
2010 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument
2048 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) local
2111 unsigned Opc = 0; local
2157 unsigned Opc = 0; local
2188 unsigned Opc = 0; local
2287 unsigned Opc = 0; local
2365 SelectAtomic64(SDNode *Node, unsigned Opc) argument
2458 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? local
2527 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) local
2616 unsigned Opc = Subtarget->isThumb() ? local
2645 unsigned Opc = 0; local
2664 unsigned Opc = 0; local
2683 unsigned Opc = 0; local
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
H A DSystemZInstrInfo.h99 SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
101 const MCInstrDesc& getLongDispOpc(unsigned Opc) const;
103 const MCInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const { argument
105 return getLongDispOpc(Opc);
107 return get(Opc);
H A DSystemZInstrInfo.cpp51 unsigned Opc = 0; local
54 Opc = SystemZ::MOV32mr;
57 Opc = SystemZ::MOV64mr;
59 Opc = SystemZ::FMOV32mr;
61 Opc = SystemZ::FMOV64mr;
63 Opc = SystemZ::MOV64Pmr;
65 Opc = SystemZ::MOV128mr;
69 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
81 unsigned Opc = 0; local
84 Opc
106 unsigned Opc; local
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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp331 unsigned Opc = Subtarget->hasAddr64() ? local
334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
531 unsigned Opc = Subtarget->hasAddr64() ? local
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
547 unsigned Opc = Subtarget->hasAddr64() ? local
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
581 unsigned Opc; local
588 Opc = WebAssembly::ARGUMENT_I32;
592 Opc = WebAssembly::ARGUMENT_I64;
596 Opc
635 unsigned Opc; local
735 unsigned Opc; local
822 unsigned Opc; local
890 unsigned Opc; local
982 unsigned Opc; local
1035 unsigned Opc; local
1098 unsigned Opc = WebAssembly::BR_IF; local
1123 unsigned Opc; local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp61 static bool IsConditionalBranch(int Opc) { argument
62 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
63 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
67 static bool IsUnconditionalJump(int Opc) { argument
68 return (Opc == Hexagon::J2_jump);
115 int Opc = MI.getOpcode(); local
116 if (IsConditionalBranch(Opc)) {
H A DHexagonSplitConst32AndConst64.cpp90 int Opc = MI.getOpcode(); local
91 if (Opc == Hexagon::CONST32_Int_Real &&
106 else if (Opc == Hexagon::CONST32_Int_Real ||
107 Opc == Hexagon::CONST32_Float_Real) {
113 if (Opc == Hexagon::CONST32_Float_Real) {
126 else if (Opc == Hexagon::CONST64_Int_Real ||
127 Opc == Hexagon::CONST64_Float_Real) {
133 if (Opc == Hexagon::CONST64_Float_Real) {
/external/llvm/include/llvm/IR/
H A DAutoUpgrade.h60 Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
66 Value *UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy);
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp310 unsigned Opc = 0; local
326 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
336 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
353 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
359 assert(Opc && SrcOpNum && "Missing parameters");
363 return Opc;
491 unsigned Opc = 0; local
496 Opc = AArch64::CSELXr;
500 Opc = AArch64::CSELWr;
504 Opc
896 unsigned Opc = CmpInstr.getOpcode(); local
1706 scaleOffset(unsigned Opc, int64_t &Offset) argument
2191 unsigned Opc = 0; local
2295 unsigned Opc = 0; local
2766 isCombineInstrSettingFlag(unsigned Opc) argument
2785 isCombineInstrCandidate32(unsigned Opc) argument
2804 isCombineInstrCandidate64(unsigned Opc) argument
2843 isCombineInstrCandidate(unsigned Opc) argument
2921 unsigned Opc = Root.getOpcode(); local
3393 unsigned Opc; local
3915 unsigned Opc = (Imm < 32) local
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H A DAArch64ConditionOptimizer.cpp206 static int getComplementOpc(int Opc) { argument
207 switch (Opc) {
233 unsigned Opc = CmpMI->getOpcode(); local
237 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
252 Opc = getComplementOpc(Opc);
255 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
262 unsigned Opc; local
264 std::tie(Imm, Opc, Cm
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H A DAArch64ConditionalCompares.cpp577 unsigned Opc = 0; local
581 Opc = AArch64::SUBSWri;
585 Opc = AArch64::SUBSXri;
590 const MCInstrDesc &MCID = TII->get(Opc);
609 unsigned Opc = 0; local
615 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break;
616 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break;
617 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break;
618 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break;
619 case AArch64::ADDSWri: Opc
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H A DAArch64RedundantCopyElimination.cpp71 unsigned Opc = MI.getOpcode(); local
74 if ((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
77 else if ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &&
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
129 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
357 unsigned Opc = 0; local
363 Opc = X86::MOV8rm;
367 Opc = X86::MOV16rm;
371 Opc = X86::MOV32rm;
376 Opc = X86::MOV64rm;
381 Opc = HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
384 Opc = X86::LD_Fp32m;
390 Opc
510 unsigned Opc = 0; local
658 unsigned Opc = 0; local
695 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
756 unsigned Opc = 0; local
1491 unsigned Opc = X86::getSETFromCond(CC); local
2044 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize()); local
2097 unsigned *Opc = nullptr; local
2163 unsigned Opc; local
2335 unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; local
2346 unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr; local
2516 unsigned Opc; local
2658 unsigned Opc; local
2753 static const uint16_t Opc[2][4] = { local
2854 unsigned Opc; local
3382 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; local
3507 unsigned Opc = 0; local
3545 unsigned Opc = 0; local
3637 unsigned Opc = local
3682 unsigned Opc = local
3699 unsigned Opc = 0; local
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp114 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
465 unsigned Opc; local
489 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
492 Opc = (IsZExt ?
497 Opc = (IsZExt ?
500 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
504 Opc = PPC::LD;
510 Opc = PPC::LFS;
513 Opc
622 unsigned Opc; local
1053 unsigned Opc; local
1147 unsigned Opc; local
1189 unsigned Opc; local
1723 unsigned Opc; local
1917 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; local
2118 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; local
2265 fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) argument
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