/external/llvm/test/MC/AArch64/ |
H A D | cyclone-crc.s | 16 crc32cb w5, w10, w15 21 CHECK: crc32cb w5, w10, w15
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H A D | arm64-leaf-compact-unwind.s | 146 ldr w15, [x8] 163 add w9, w9, w15
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H A D | basic-a64-instructions.s | 37 add w21, w15, w17, uxth 45 // CHECK: add w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x0b] 82 sub w21, w15, w17, uxth 90 // CHECK: sub w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x4b] 117 adds w21, w15, w17, uxth 125 // CHECK: adds w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x2b] 152 subs w21, w15, w17, uxth 160 // CHECK: subs w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x6b] 187 cmp w15, w17, uxth 195 // CHECK: cmp w15, w1 [all...] |
/external/llvm/test/MC/Mips/ |
H A D | set-push-pop-directives.s | 11 addvi.b $w15, $w13, 18 27 addvi.b $w15, $w13, 18 34 # CHECK: addvi.b $w15, $w13, 18 53 # CHECK: addvi.b $w15, $w13, 18
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/external/capstone/suite/MC/Mips/ |
H A D | test_2rf.s.cs | 9 0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15 15 0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15 18 0x7b,0x2c,0x79,0xde = frint.w $w7, $w15 25 0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12 32 0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15
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H A D | test_vec.s.cs | 8 0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15
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H A D | test_3r.s.cs | 9 0x78,0xfa,0x93,0xd0 = adds_a.d $w15, $w18, $w26 16 0x79,0xd4,0x93,0xd0 = adds_u.w $w15, $w18, $w20 27 0x7a,0xaf,0x4c,0x91 = asub_u.h $w18, $w9, $w15 46 0x79,0x9d,0x78,0x8d = bclr.b $w2, $w15, $w29 52 0x7b,0x4d,0x7b,0x8d = binsl.w $w14, $w15, $w13 61 0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15 98 0x78,0xd5,0xb3,0xd3 = dotp_u.w $w15, $w22, $w21 105 0x79,0xf0,0xeb,0xd3 = dpadd_u.d $w15, $w29, $w16 114 0x7a,0x74,0x7c,0x55 = hadd_s.d $w17, $w15, $w20 149 0x79,0x31,0xeb,0xce = max_s.h $w15, [all...] |
H A D | test_i5.s.cs | 7 0x78,0x22,0x7f,0xc7 = ceqi.h $w31, $w15, 2 19 0x79,0x34,0x53,0xc7 = clti_s.h $w15, $w10, -12 41 0x7a,0xe2,0x7a,0xc6 = mini_u.d $w11, $w15, 2
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H A D | test_mi10.s.cs | 17 0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($16)
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H A D | test_bit.s.cs | 10 0x7b,0xf0,0x9b,0xc9 = binsri.b $w15, $w19, 0 21 0x7a,0x01,0x79,0xc9 = bseti.d $w7, $w15, 1
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H A D | test_3rf.s.cs | 13 0x78,0xef,0xa3,0x9c = fcne.d $w14, $w20, $w15 44 0x78,0x8f,0x78,0xdb = fmul.w $w3, $w15, $w15
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/external/llvm/test/MC/Mips/msa/ |
H A D | test_2rf.s | 10 # CHECK: ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e] 16 # CHECK: ffqr.d $w30, $w15 # encoding: [0x7b,0x37,0x7f,0x9e] 19 # CHECK: frint.w $w7, $w15 # encoding: [0x7b,0x2c,0x79,0xde] 26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde] 33 # CHECK: ftrunc_u.w $w17, $w15 # encoding: [0x7b,0x24,0x7c,0x5e] 43 ffint_s.d $w12, $w15 49 ffqr.d $w30, $w15 52 frint.w $w7, $w15 59 fsqrt.d $w15, $w12 66 ftrunc_u.w $w17, $w15 [all...] |
H A D | test_vec.s | 9 # CHECK: xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde] 17 xor.v $w7, $w27, $w15
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H A D | test_3r.s | 10 # CHECK: adds_a.d $w15, $w18, $w26 # encoding: [0x78,0xfa,0x93,0xd0] 17 # CHECK: adds_u.w $w15, $w18, $w20 # encoding: [0x79,0xd4,0x93,0xd0] 28 # CHECK: asub_u.h $w18, $w9, $w15 # encoding: [0x7a,0xaf,0x4c,0x91] 47 # CHECK: bclr.b $w2, $w15, $w29 # encoding: [0x79,0x9d,0x78,0x8d] 53 # CHECK: binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d] 62 # CHECK: bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d] 99 # CHECK: dotp_u.w $w15, $w22, $w21 # encoding: [0x78,0xd5,0xb3,0xd3] 106 # CHECK: dpadd_u.d $w15, $w29, $w16 # encoding: [0x79,0xf0,0xeb,0xd3] 115 # CHECK: hadd_s.d $w17, $w15, $w20 # encoding: [0x7a,0x74,0x7c,0x55] 150 # CHECK: max_s.h $w15, [all...] |
H A D | test_i5.s | 8 # CHECK: ceqi.h $w31, $w15, 2 # encoding: [0x78,0x22,0x7f,0xc7] 20 # CHECK: clti_s.h $w15, $w10, -12 # encoding: [0x79,0x34,0x53,0xc7] 42 # CHECK: mini_u.d $w11, $w15, 2 # encoding: [0x7a,0xe2,0x7a,0xc6] 53 ceqi.h $w31, $w15, 2 65 clti_s.h $w15, $w10, -12 87 mini_u.d $w11, $w15, 2
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H A D | test_mi10.s | 21 ld.d $w15, -2048($16) # CHECK: ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
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H A D | test_3rf.s | 14 # CHECK: fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c] 45 # CHECK: fmul.w $w3, $w15, $w15 # encoding: [0x78,0x8f,0x78,0xdb] 97 fcne.d $w14, $w20, $w15 128 fmul.w $w3, $w15, $w15
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H A D | test_bit.s | 11 # CHECK: binsri.b $w15, $w19, 0 # encoding: [0x7b,0xf0,0x9b,0xc9] 22 # CHECK: bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9] 60 binsri.b $w15, $w19, 0 71 bseti.d $w7, $w15, 1
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/external/boringssl/ios-aarch64/crypto/fipsmodule/ |
H A D | sha1-armv8.S | 194 add w22,w22,w15 // future e+=X[i] 278 eor w7,w7,w15 350 eor w13,w13,w15 374 eor w15,w15,w17 378 eor w15,w15,w7 382 eor w15,w15,w12 385 ror w15,w1 [all...] |
H A D | sha256-armv8.S | 313 eor w15,w23,w23,ror#14 319 eor w16,w16,w15,ror#11 // Sigma1(e) 320 ror w15,w27,#2 327 eor w17,w15,w17,ror#13 // Sigma0(a) 358 ldp w15,w0,[x1],#2*4 382 rev w15,w15 // 12 391 add w23,w23,w15 // h+=X[i] 580 add w6,w6,w15 619 str w15,[s [all...] |
/external/boringssl/linux-aarch64/crypto/fipsmodule/ |
H A D | sha1-armv8.S | 195 add w22,w22,w15 // future e+=X[i] 279 eor w7,w7,w15 351 eor w13,w13,w15 375 eor w15,w15,w17 379 eor w15,w15,w7 383 eor w15,w15,w12 386 ror w15,w1 [all...] |
H A D | sha256-armv8.S | 314 eor w15,w23,w23,ror#14 320 eor w16,w16,w15,ror#11 // Sigma1(e) 321 ror w15,w27,#2 328 eor w17,w15,w17,ror#13 // Sigma0(a) 359 ldp w15,w0,[x1],#2*4 383 rev w15,w15 // 12 392 add w23,w23,w15 // h+=X[i] 581 add w6,w6,w15 620 str w15,[s [all...] |
/external/boringssl/ios-aarch64/crypto/chacha/ |
H A D | chacha-armv8.S | 75 mov w15,w27 100 add w15,w15,w20 104 eor w11,w11,w15 124 add w15,w15,w20 128 eor w11,w11,w15 146 add w15,w15,w21 150 eor w10,w10,w15 [all...] |
/external/boringssl/linux-aarch64/crypto/chacha/ |
H A D | chacha-armv8.S | 76 mov w15,w27 101 add w15,w15,w20 105 eor w11,w11,w15 125 add w15,w15,w20 129 eor w11,w11,w15 147 add w15,w15,w21 151 eor w10,w10,w15 [all...] |
/external/llvm/test/MC/Mips/mips32r2/ |
H A D | invalid-msa.s | 9 bmnz.v $w15,$w2,$w28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 16 fexupr.d $w31,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 38 fsqrt.w $w5,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 56 nor.v $w20,$w20,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 58 pcnt.b $w30,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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