11452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee%default {"preinstr":""} 21452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee /* 31452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * Generic 64-bit unary operation. Provide an "instr" line that 41452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * specifies an instruction that performs "result = op r0/r1". 51452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * This could be an ARM instruction or a function call. 61452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * 71452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee * For: neg-long, not-long, neg-double, long-to-double, double-to-long 81452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee */ 91452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee /* unop vA, vB */ 101452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee mov r3, rINST, lsr #12 @ r3<- B 1150cf600419109c9cbb0686edc6f7456c13ef7f08buzbee ubfx rINST, rINST, #8, #4 @ rINST<- A 12ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 13ace690f5e440930d7bbad97fdbfdc3eb65e230bebuzbee VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 141452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee ldmia r3, {r0-r1} @ r0/r1<- vAA 1550cf600419109c9cbb0686edc6f7456c13ef7f08buzbee CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 161452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 171452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee $preinstr @ optional op; may set condition codes 181452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee $instr @ r0/r1<- op, r2-r3 changed 191452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee GET_INST_OPCODE ip @ extract opcode from rINST 201452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee stmia r9, {r0-r1} @ vAA<- r0/r1 211452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee GOTO_OPCODE ip @ jump to next instruction 221452bee8f06b9f76a333ddf4760e4beaa82f8099buzbee /* 10-11 instructions */ 23