1200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 2200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit "/2addr" binary operation. Provide an "instr" 384603bf8535ba8390e0461b9d9c7917939e26312Alexey Frunze * that specifies an instruction that performs "fv0 = fa0 op fa1". 4200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be an MIPS instruction or a function call. 5200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 6200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 784603bf8535ba8390e0461b9d9c7917939e26312Alexey Frunze * div-float/2addr, rem-float/2addr 8200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 9200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop/2addr vA, vB */ 1084603bf8535ba8390e0461b9d9c7917939e26312Alexey Frunze GET_OPA4(rOBJ) # rOBJ <- A+ 11200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPB(a3) # a3 <- B 12200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa0, rOBJ) 13200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG_F(fa1, a3) 14200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(1) # advance rPC, load rINST 15200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 16200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung $instr 17200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 1884603bf8535ba8390e0461b9d9c7917939e26312Alexey Frunze SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result 19