kvm.h revision 96c1db7b9d601c31d103389cac074a6cce0d7633
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _ASM_X86_KVM_H 20#define _ASM_X86_KVM_H 21#include <linux/types.h> 22#include <linux/ioctl.h> 23#define DE_VECTOR 0 24#define DB_VECTOR 1 25#define BP_VECTOR 3 26#define OF_VECTOR 4 27#define BR_VECTOR 5 28#define UD_VECTOR 6 29#define NM_VECTOR 7 30#define DF_VECTOR 8 31#define TS_VECTOR 10 32#define NP_VECTOR 11 33#define SS_VECTOR 12 34#define GP_VECTOR 13 35#define PF_VECTOR 14 36#define MF_VECTOR 16 37#define AC_VECTOR 17 38#define MC_VECTOR 18 39#define XM_VECTOR 19 40#define VE_VECTOR 20 41#define __KVM_HAVE_PIT 42#define __KVM_HAVE_IOAPIC 43#define __KVM_HAVE_IRQ_LINE 44#define __KVM_HAVE_MSI 45#define __KVM_HAVE_USER_NMI 46#define __KVM_HAVE_GUEST_DEBUG 47#define __KVM_HAVE_MSIX 48#define __KVM_HAVE_MCE 49#define __KVM_HAVE_PIT_STATE2 50#define __KVM_HAVE_XEN_HVM 51#define __KVM_HAVE_VCPU_EVENTS 52#define __KVM_HAVE_DEBUGREGS 53#define __KVM_HAVE_XSAVE 54#define __KVM_HAVE_XCRS 55#define __KVM_HAVE_READONLY_MEM 56#define KVM_NR_INTERRUPTS 256 57struct kvm_memory_alias { 58 __u32 slot; 59 __u32 flags; 60 __u64 guest_phys_addr; 61 __u64 memory_size; 62 __u64 target_phys_addr; 63}; 64struct kvm_pic_state { 65 __u8 last_irr; 66 __u8 irr; 67 __u8 imr; 68 __u8 isr; 69 __u8 priority_add; 70 __u8 irq_base; 71 __u8 read_reg_select; 72 __u8 poll; 73 __u8 special_mask; 74 __u8 init_state; 75 __u8 auto_eoi; 76 __u8 rotate_on_auto_eoi; 77 __u8 special_fully_nested_mode; 78 __u8 init4; 79 __u8 elcr; 80 __u8 elcr_mask; 81}; 82#define KVM_IOAPIC_NUM_PINS 24 83struct kvm_ioapic_state { 84 __u64 base_address; 85 __u32 ioregsel; 86 __u32 id; 87 __u32 irr; 88 __u32 pad; 89 union { 90 __u64 bits; 91 struct { 92 __u8 vector; 93 __u8 delivery_mode : 3; 94 __u8 dest_mode : 1; 95 __u8 delivery_status : 1; 96 __u8 polarity : 1; 97 __u8 remote_irr : 1; 98 __u8 trig_mode : 1; 99 __u8 mask : 1; 100 __u8 reserve : 7; 101 __u8 reserved[4]; 102 __u8 dest_id; 103 } fields; 104 } redirtbl[KVM_IOAPIC_NUM_PINS]; 105}; 106#define KVM_IRQCHIP_PIC_MASTER 0 107#define KVM_IRQCHIP_PIC_SLAVE 1 108#define KVM_IRQCHIP_IOAPIC 2 109#define KVM_NR_IRQCHIPS 3 110#define KVM_RUN_X86_SMM (1 << 0) 111struct kvm_regs { 112 __u64 rax, rbx, rcx, rdx; 113 __u64 rsi, rdi, rsp, rbp; 114 __u64 r8, r9, r10, r11; 115 __u64 r12, r13, r14, r15; 116 __u64 rip, rflags; 117}; 118#define KVM_APIC_REG_SIZE 0x400 119struct kvm_lapic_state { 120 char regs[KVM_APIC_REG_SIZE]; 121}; 122struct kvm_segment { 123 __u64 base; 124 __u32 limit; 125 __u16 selector; 126 __u8 type; 127 __u8 present, dpl, db, s, l, g, avl; 128 __u8 unusable; 129 __u8 padding; 130}; 131struct kvm_dtable { 132 __u64 base; 133 __u16 limit; 134 __u16 padding[3]; 135}; 136struct kvm_sregs { 137 struct kvm_segment cs, ds, es, fs, gs, ss; 138 struct kvm_segment tr, ldt; 139 struct kvm_dtable gdt, idt; 140 __u64 cr0, cr2, cr3, cr4, cr8; 141 __u64 efer; 142 __u64 apic_base; 143 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 144}; 145struct kvm_fpu { 146 __u8 fpr[8][16]; 147 __u16 fcw; 148 __u16 fsw; 149 __u8 ftwx; 150 __u8 pad1; 151 __u16 last_opcode; 152 __u64 last_ip; 153 __u64 last_dp; 154 __u8 xmm[16][16]; 155 __u32 mxcsr; 156 __u32 pad2; 157}; 158struct kvm_msr_entry { 159 __u32 index; 160 __u32 reserved; 161 __u64 data; 162}; 163struct kvm_msrs { 164 __u32 nmsrs; 165 __u32 pad; 166 struct kvm_msr_entry entries[0]; 167}; 168struct kvm_msr_list { 169 __u32 nmsrs; 170 __u32 indices[0]; 171}; 172struct kvm_cpuid_entry { 173 __u32 function; 174 __u32 eax; 175 __u32 ebx; 176 __u32 ecx; 177 __u32 edx; 178 __u32 padding; 179}; 180struct kvm_cpuid { 181 __u32 nent; 182 __u32 padding; 183 struct kvm_cpuid_entry entries[0]; 184}; 185struct kvm_cpuid_entry2 { 186 __u32 function; 187 __u32 index; 188 __u32 flags; 189 __u32 eax; 190 __u32 ebx; 191 __u32 ecx; 192 __u32 edx; 193 __u32 padding[3]; 194}; 195#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) 196#define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) 197#define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) 198struct kvm_cpuid2 { 199 __u32 nent; 200 __u32 padding; 201 struct kvm_cpuid_entry2 entries[0]; 202}; 203struct kvm_pit_channel_state { 204 __u32 count; 205 __u16 latched_count; 206 __u8 count_latched; 207 __u8 status_latched; 208 __u8 status; 209 __u8 read_state; 210 __u8 write_state; 211 __u8 write_latch; 212 __u8 rw_mode; 213 __u8 mode; 214 __u8 bcd; 215 __u8 gate; 216 __s64 count_load_time; 217}; 218struct kvm_debug_exit_arch { 219 __u32 exception; 220 __u32 pad; 221 __u64 pc; 222 __u64 dr6; 223 __u64 dr7; 224}; 225#define KVM_GUESTDBG_USE_SW_BP 0x00010000 226#define KVM_GUESTDBG_USE_HW_BP 0x00020000 227#define KVM_GUESTDBG_INJECT_DB 0x00040000 228#define KVM_GUESTDBG_INJECT_BP 0x00080000 229struct kvm_guest_debug_arch { 230 __u64 debugreg[8]; 231}; 232struct kvm_pit_state { 233 struct kvm_pit_channel_state channels[3]; 234}; 235#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 236struct kvm_pit_state2 { 237 struct kvm_pit_channel_state channels[3]; 238 __u32 flags; 239 __u32 reserved[9]; 240}; 241struct kvm_reinject_control { 242 __u8 pit_reinject; 243 __u8 reserved[31]; 244}; 245#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 246#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 247#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 248#define KVM_VCPUEVENT_VALID_SMM 0x00000008 249#define KVM_X86_SHADOW_INT_MOV_SS 0x01 250#define KVM_X86_SHADOW_INT_STI 0x02 251struct kvm_vcpu_events { 252 struct { 253 __u8 injected; 254 __u8 nr; 255 __u8 has_error_code; 256 __u8 pad; 257 __u32 error_code; 258 } exception; 259 struct { 260 __u8 injected; 261 __u8 nr; 262 __u8 soft; 263 __u8 shadow; 264 } interrupt; 265 struct { 266 __u8 injected; 267 __u8 pending; 268 __u8 masked; 269 __u8 pad; 270 } nmi; 271 __u32 sipi_vector; 272 __u32 flags; 273 struct { 274 __u8 smm; 275 __u8 pending; 276 __u8 smm_inside_nmi; 277 __u8 latched_init; 278 } smi; 279 __u32 reserved[9]; 280}; 281struct kvm_debugregs { 282 __u64 db[4]; 283 __u64 dr6; 284 __u64 dr7; 285 __u64 flags; 286 __u64 reserved[9]; 287}; 288struct kvm_xsave { 289 __u32 region[1024]; 290}; 291#define KVM_MAX_XCRS 16 292struct kvm_xcr { 293 __u32 xcr; 294 __u32 reserved; 295 __u64 value; 296}; 297struct kvm_xcrs { 298 __u32 nr_xcrs; 299 __u32 flags; 300 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 301 __u64 padding[16]; 302}; 303struct kvm_sync_regs { 304}; 305#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) 306#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) 307#endif 308