amdgpu_drm.h revision 05d08e9716b5974d6ed08973f44930804890b902
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef __AMDGPU_DRM_H__ 20#define __AMDGPU_DRM_H__ 21#include "drm.h" 22#define DRM_AMDGPU_GEM_CREATE 0x00 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#define DRM_AMDGPU_GEM_MMAP 0x01 25#define DRM_AMDGPU_CTX 0x02 26#define DRM_AMDGPU_BO_LIST 0x03 27#define DRM_AMDGPU_CS 0x04 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define DRM_AMDGPU_INFO 0x05 30#define DRM_AMDGPU_GEM_METADATA 0x06 31#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 32#define DRM_AMDGPU_GEM_VA 0x08 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define DRM_AMDGPU_WAIT_CS 0x09 35#define DRM_AMDGPU_GEM_OP 0x10 36#define DRM_AMDGPU_GEM_USERPTR 0x11 37#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 40#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 41#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 42#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 45#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 46#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 47#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 50#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 51#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 52#define AMDGPU_GEM_DOMAIN_CPU 0x1 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define AMDGPU_GEM_DOMAIN_GTT 0x2 55#define AMDGPU_GEM_DOMAIN_VRAM 0x4 56#define AMDGPU_GEM_DOMAIN_GDS 0x8 57#define AMDGPU_GEM_DOMAIN_GWS 0x10 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define AMDGPU_GEM_DOMAIN_OA 0x20 60#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 61#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 62#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64struct drm_amdgpu_gem_create_in { 65 uint64_t bo_size; 66 uint64_t alignment; 67 uint64_t domains; 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 uint64_t domain_flags; 70}; 71struct drm_amdgpu_gem_create_out { 72 uint32_t handle; 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 uint32_t _pad; 75}; 76union drm_amdgpu_gem_create { 77 struct drm_amdgpu_gem_create_in in; 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 struct drm_amdgpu_gem_create_out out; 80}; 81#define AMDGPU_BO_LIST_OP_CREATE 0 82#define AMDGPU_BO_LIST_OP_DESTROY 1 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define AMDGPU_BO_LIST_OP_UPDATE 2 85struct drm_amdgpu_bo_list_in { 86 uint32_t operation; 87 uint32_t list_handle; 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 uint32_t bo_number; 90 uint32_t bo_info_size; 91 uint64_t bo_info_ptr; 92}; 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94struct drm_amdgpu_bo_list_entry { 95 uint32_t bo_handle; 96 uint32_t bo_priority; 97}; 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99struct drm_amdgpu_bo_list_out { 100 uint32_t list_handle; 101 uint32_t _pad; 102}; 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104union drm_amdgpu_bo_list { 105 struct drm_amdgpu_bo_list_in in; 106 struct drm_amdgpu_bo_list_out out; 107}; 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define AMDGPU_CTX_OP_ALLOC_CTX 1 110#define AMDGPU_CTX_OP_FREE_CTX 2 111#define AMDGPU_CTX_OP_QUERY_STATE 3 112#define AMDGPU_CTX_NO_RESET 0 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define AMDGPU_CTX_GUILTY_RESET 1 115#define AMDGPU_CTX_INNOCENT_RESET 2 116#define AMDGPU_CTX_UNKNOWN_RESET 3 117struct drm_amdgpu_ctx_in { 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 uint32_t op; 120 uint32_t flags; 121 uint32_t ctx_id; 122 uint32_t _pad; 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124}; 125union drm_amdgpu_ctx_out { 126 struct { 127 uint32_t ctx_id; 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 uint32_t _pad; 130 } alloc; 131 struct { 132 uint64_t flags; 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 uint32_t hangs; 135 uint32_t reset_status; 136 } state; 137}; 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139union drm_amdgpu_ctx { 140 struct drm_amdgpu_ctx_in in; 141 union drm_amdgpu_ctx_out out; 142}; 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 145#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 146#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 147#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149struct drm_amdgpu_gem_userptr { 150 uint64_t addr; 151 uint64_t size; 152 uint32_t flags; 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 uint32_t handle; 155}; 156#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 157#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 160#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 161#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 162#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 165#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 166#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 167#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 170#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 171#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 172#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 175#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 176#define AMDGPU_TILING_SET(field,value) (((value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 177#define AMDGPU_TILING_GET(value,field) (((value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 180#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 181struct drm_amdgpu_gem_metadata { 182 uint32_t handle; 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 uint32_t op; 185 struct { 186 uint64_t flags; 187 uint64_t tiling_info; 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 uint32_t data_size_bytes; 190 uint32_t data[64]; 191 } data; 192}; 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194struct drm_amdgpu_gem_mmap_in { 195 uint32_t handle; 196 uint32_t _pad; 197}; 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199struct drm_amdgpu_gem_mmap_out { 200 uint64_t addr_ptr; 201}; 202union drm_amdgpu_gem_mmap { 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 struct drm_amdgpu_gem_mmap_in in; 205 struct drm_amdgpu_gem_mmap_out out; 206}; 207struct drm_amdgpu_gem_wait_idle_in { 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 uint32_t handle; 210 uint32_t flags; 211 uint64_t timeout; 212}; 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214struct drm_amdgpu_gem_wait_idle_out { 215 uint32_t status; 216 uint32_t domain; 217}; 218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219union drm_amdgpu_gem_wait_idle { 220 struct drm_amdgpu_gem_wait_idle_in in; 221 struct drm_amdgpu_gem_wait_idle_out out; 222}; 223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224struct drm_amdgpu_wait_cs_in { 225 uint64_t handle; 226 uint64_t timeout; 227 uint32_t ip_type; 228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 uint32_t ip_instance; 230 uint32_t ring; 231 uint32_t ctx_id; 232}; 233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234struct drm_amdgpu_wait_cs_out { 235 uint64_t status; 236}; 237union drm_amdgpu_wait_cs { 238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 struct drm_amdgpu_wait_cs_in in; 240 struct drm_amdgpu_wait_cs_out out; 241}; 242#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244#define AMDGPU_GEM_OP_SET_PLACEMENT 1 245struct drm_amdgpu_gem_op { 246 uint32_t handle; 247 uint32_t op; 248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 uint64_t value; 250}; 251#define AMDGPU_VA_OP_MAP 1 252#define AMDGPU_VA_OP_UNMAP 2 253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 255#define AMDGPU_VM_PAGE_READABLE (1 << 1) 256#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 257#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259struct drm_amdgpu_gem_va { 260 uint32_t handle; 261 uint32_t _pad; 262 uint32_t operation; 263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 uint32_t flags; 265 uint64_t va_address; 266 uint64_t offset_in_bo; 267 uint64_t map_size; 268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269}; 270#define AMDGPU_HW_IP_GFX 0 271#define AMDGPU_HW_IP_COMPUTE 1 272#define AMDGPU_HW_IP_DMA 2 273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274#define AMDGPU_HW_IP_UVD 3 275#define AMDGPU_HW_IP_VCE 4 276#define AMDGPU_HW_IP_NUM 5 277#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279#define AMDGPU_CHUNK_ID_IB 0x01 280#define AMDGPU_CHUNK_ID_FENCE 0x02 281#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 282struct drm_amdgpu_cs_chunk { 283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 uint32_t chunk_id; 285 uint32_t length_dw; 286 uint64_t chunk_data; 287}; 288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289struct drm_amdgpu_cs_in { 290 uint32_t ctx_id; 291 uint32_t bo_list_handle; 292 uint32_t num_chunks; 293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 uint32_t _pad; 295 uint64_t chunks; 296}; 297struct drm_amdgpu_cs_out { 298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 uint64_t handle; 300}; 301union drm_amdgpu_cs { 302 struct drm_amdgpu_cs_in in; 303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 struct drm_amdgpu_cs_out out; 305}; 306#define AMDGPU_IB_FLAG_CE (1 << 0) 307#define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309struct drm_amdgpu_cs_chunk_ib { 310 uint32_t _pad; 311 uint32_t flags; 312 uint64_t va_start; 313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 uint32_t ib_bytes; 315 uint32_t ip_type; 316 uint32_t ip_instance; 317 uint32_t ring; 318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319}; 320struct drm_amdgpu_cs_chunk_dep { 321 uint32_t ip_type; 322 uint32_t ip_instance; 323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 uint32_t ring; 325 uint32_t ctx_id; 326 uint64_t handle; 327}; 328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329struct drm_amdgpu_cs_chunk_fence { 330 uint32_t handle; 331 uint32_t offset; 332}; 333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334struct drm_amdgpu_cs_chunk_data { 335 union { 336 struct drm_amdgpu_cs_chunk_ib ib_data; 337 struct drm_amdgpu_cs_chunk_fence fence_data; 338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 }; 340}; 341#define AMDGPU_IDS_FLAGS_FUSION 0x1 342#define AMDGPU_INFO_ACCEL_WORKING 0x00 343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344#define AMDGPU_INFO_CRTC_FROM_ID 0x01 345#define AMDGPU_INFO_HW_IP_INFO 0x02 346#define AMDGPU_INFO_HW_IP_COUNT 0x03 347#define AMDGPU_INFO_TIMESTAMP 0x05 348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349#define AMDGPU_INFO_FW_VERSION 0x0e 350#define AMDGPU_INFO_FW_VCE 0x1 351#define AMDGPU_INFO_FW_UVD 0x2 352#define AMDGPU_INFO_FW_GMC 0x03 353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354#define AMDGPU_INFO_FW_GFX_ME 0x04 355#define AMDGPU_INFO_FW_GFX_PFP 0x05 356#define AMDGPU_INFO_FW_GFX_CE 0x06 357#define AMDGPU_INFO_FW_GFX_RLC 0x07 358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359#define AMDGPU_INFO_FW_GFX_MEC 0x08 360#define AMDGPU_INFO_FW_SMC 0x0a 361#define AMDGPU_INFO_FW_SDMA 0x0b 362#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364#define AMDGPU_INFO_VRAM_USAGE 0x10 365#define AMDGPU_INFO_GTT_USAGE 0x11 366#define AMDGPU_INFO_GDS_CONFIG 0x13 367#define AMDGPU_INFO_VRAM_GTT 0x14 368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369#define AMDGPU_INFO_READ_MMR_REG 0x15 370#define AMDGPU_INFO_DEV_INFO 0x16 371#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 372#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 375#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 376#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 377struct drm_amdgpu_info { 378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 uint64_t return_pointer; 380 uint32_t return_size; 381 uint32_t query; 382 union { 383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 struct { 385 uint32_t id; 386 uint32_t _pad; 387 } mode_crtc; 388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 struct { 390 uint32_t type; 391 uint32_t ip_instance; 392 } query_hw_ip; 393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 struct { 395 uint32_t dword_offset; 396 uint32_t count; 397 uint32_t instance; 398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 uint32_t flags; 400 } read_mmr_reg; 401 struct { 402 uint32_t fw_type; 403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 uint32_t ip_instance; 405 uint32_t index; 406 uint32_t _pad; 407 } query_fw; 408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 }; 410}; 411struct drm_amdgpu_info_gds { 412 uint32_t gds_gfx_partition_size; 413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 uint32_t compute_partition_size; 415 uint32_t gds_total_size; 416 uint32_t gws_per_gfx_partition; 417 uint32_t gws_per_compute_partition; 418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 uint32_t oa_per_gfx_partition; 420 uint32_t oa_per_compute_partition; 421 uint32_t _pad; 422}; 423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424struct drm_amdgpu_info_vram_gtt { 425 uint64_t vram_size; 426 uint64_t vram_cpu_accessible_size; 427 uint64_t gtt_size; 428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429}; 430struct drm_amdgpu_info_firmware { 431 uint32_t ver; 432 uint32_t feature; 433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434}; 435#define AMDGPU_VRAM_TYPE_UNKNOWN 0 436#define AMDGPU_VRAM_TYPE_GDDR1 1 437#define AMDGPU_VRAM_TYPE_DDR2 2 438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439#define AMDGPU_VRAM_TYPE_GDDR3 3 440#define AMDGPU_VRAM_TYPE_GDDR4 4 441#define AMDGPU_VRAM_TYPE_GDDR5 5 442#define AMDGPU_VRAM_TYPE_HBM 6 443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444#define AMDGPU_VRAM_TYPE_DDR3 7 445struct drm_amdgpu_info_device { 446 uint32_t device_id; 447 uint32_t chip_rev; 448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 uint32_t external_rev; 450 uint32_t pci_rev; 451 uint32_t family; 452 uint32_t num_shader_engines; 453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 uint32_t num_shader_arrays_per_engine; 455 uint32_t gpu_counter_freq; 456 uint64_t max_engine_clock; 457 uint64_t max_memory_clock; 458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 uint32_t cu_active_number; 460 uint32_t cu_ao_mask; 461 uint32_t cu_bitmap[4][4]; 462 uint32_t enabled_rb_pipes_mask; 463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 uint32_t num_rb_pipes; 465 uint32_t num_hw_gfx_contexts; 466 uint32_t _pad; 467 uint64_t ids_flags; 468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 uint64_t virtual_address_offset; 470 uint64_t virtual_address_max; 471 uint32_t virtual_address_alignment; 472 uint32_t pte_fragment_size; 473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 uint32_t gart_page_size; 475 uint32_t ce_ram_size; 476 uint32_t vram_type; 477 uint32_t vram_bit_width; 478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 uint32_t vce_harvest_config; 480}; 481struct drm_amdgpu_info_hw_ip { 482 uint32_t hw_ip_version_major; 483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 uint32_t hw_ip_version_minor; 485 uint64_t capabilities_flags; 486 uint32_t ib_start_alignment; 487 uint32_t ib_size_alignment; 488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 uint32_t available_rings; 490 uint32_t _pad; 491}; 492#define AMDGPU_FAMILY_UNKNOWN 0 493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494#define AMDGPU_FAMILY_CI 120 495#define AMDGPU_FAMILY_KV 125 496#define AMDGPU_FAMILY_VI 130 497#define AMDGPU_FAMILY_CZ 135 498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499#endif 500